[LoopInterchange] Fix handling of LCSSA nodes defined in headers and latches.
The code to preserve LCSSA PHIs currently only properly supports reduction PHIs and PHIs for values defined outside the latches. This patch improves the LCSSA PHI handling to cover PHIs for values defined in the latches. Fixes PR41725. Reviewers: efriedma, mcrosier, davide, jdoerfert Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D61576 llvm-svn: 361743
This commit is contained in:
Florian Hahn
parent
e698958ad8
commit
11b2f4fe50
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@ -1301,8 +1301,41 @@ static void updateSuccessor(BranchInst *BI, BasicBlock *OldBB,
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}
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// Move Lcssa PHIs to the right place.
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static void moveLCSSAPhis(BasicBlock *InnerExit, BasicBlock *InnerLatch,
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BasicBlock *OuterLatch) {
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static void moveLCSSAPhis(BasicBlock *InnerExit, BasicBlock *InnerHeader,
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BasicBlock *InnerLatch, BasicBlock *OuterHeader,
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BasicBlock *OuterLatch, BasicBlock *OuterExit) {
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// Deal with LCSSA PHI nodes in the exit block of the inner loop, that are
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// defined either in the header or latch. Those blocks will become header and
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// latch of the new outer loop, and the only possible users can PHI nodes
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// in the exit block of the loop nest or the outer loop header (reduction
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// PHIs, in that case, the incoming value must be defined in the inner loop
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// header). We can just substitute the user with the incoming value and remove
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// the PHI.
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for (PHINode &P : make_early_inc_range(InnerExit->phis())) {
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assert(P.getNumIncomingValues() == 1 &&
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"Only loops with a single exit are supported!");
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// Incoming values are guaranteed be instructions currently.
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auto IncI = cast<Instruction>(P.getIncomingValueForBlock(InnerLatch));
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// Skip phis with incoming values from the inner loop body, excluding the
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// header and latch.
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if (IncI->getParent() != InnerLatch && IncI->getParent() != InnerHeader)
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continue;
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assert(all_of(P.users(),
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[OuterHeader, OuterExit, IncI, InnerHeader](User *U) {
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return (cast<PHINode>(U)->getParent() == OuterHeader &&
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IncI->getParent() == InnerHeader) ||
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cast<PHINode>(U)->getParent() == OuterExit;
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}) &&
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"Can only replace phis iff the uses are in the loop nest exit or "
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"the incoming value is defined in the inner header (it will "
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"dominate all loop blocks after interchanging)");
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P.replaceAllUsesWith(IncI);
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P.eraseFromParent();
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}
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SmallVector<PHINode *, 8> LcssaInnerExit;
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for (PHINode &P : InnerExit->phis())
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LcssaInnerExit.push_back(&P);
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@ -1315,31 +1348,39 @@ static void moveLCSSAPhis(BasicBlock *InnerExit, BasicBlock *InnerLatch,
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// If a PHI node has users outside of InnerExit, it has a use outside the
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// interchanged loop and we have to preserve it. We move these to
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// InnerLatch, which will become the new exit block for the innermost
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// loop after interchanging. For PHIs only used in InnerExit, we can just
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// replace them with the incoming value.
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for (PHINode *P : LcssaInnerExit) {
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bool hasUsersOutside = false;
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for (auto UI = P->use_begin(), E = P->use_end(); UI != E;) {
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Use &U = *UI;
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++UI;
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auto *Usr = cast<Instruction>(U.getUser());
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if (Usr->getParent() != InnerExit) {
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hasUsersOutside = true;
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continue;
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}
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U.set(P->getIncomingValueForBlock(InnerLatch));
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}
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if (hasUsersOutside)
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P->moveBefore(InnerLatch->getFirstNonPHI());
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else
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P->eraseFromParent();
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}
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// loop after interchanging.
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for (PHINode *P : LcssaInnerExit)
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P->moveBefore(InnerLatch->getFirstNonPHI());
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// If the inner loop latch contains LCSSA PHIs, those come from a child loop
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// and we have to move them to the new inner latch.
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for (PHINode *P : LcssaInnerLatch)
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P->moveBefore(InnerExit->getFirstNonPHI());
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// Deal with LCSSA PHI nodes in the loop nest exit block. For PHIs that have
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// incoming values from the outer latch or header, we have to add a new PHI
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// in the inner loop latch, which became the exit block of the outer loop,
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// after interchanging.
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if (OuterExit) {
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for (PHINode &P : OuterExit->phis()) {
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if (P.getNumIncomingValues() != 1)
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continue;
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// Skip Phis with incoming values not defined in the outer loop's header
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// and latch. Also skip incoming phis defined in the latch. Those should
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// already have been updated.
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auto I = dyn_cast<Instruction>(P.getIncomingValue(0));
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if (!I || ((I->getParent() != OuterLatch || isa<PHINode>(I)) &&
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I->getParent() != OuterHeader))
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continue;
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PHINode *NewPhi = dyn_cast<PHINode>(P.clone());
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NewPhi->setIncomingValue(0, P.getIncomingValue(0));
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NewPhi->setIncomingBlock(0, OuterLatch);
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NewPhi->insertBefore(InnerLatch->getFirstNonPHI());
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P.setIncomingValue(0, NewPhi);
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}
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}
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// Now adjust the incoming blocks for the LCSSA PHIs.
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// For PHIs moved from Inner's exit block, we need to replace Inner's latch
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// with the new latch.
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@ -1442,7 +1483,8 @@ bool LoopInterchangeTransform::adjustLoopBranches() {
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restructureLoops(OuterLoop, InnerLoop, InnerLoopPreHeader,
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OuterLoopPreHeader);
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moveLCSSAPhis(InnerLoopLatchSuccessor, InnerLoopLatch, OuterLoopLatch);
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moveLCSSAPhis(InnerLoopLatchSuccessor, InnerLoopHeader, InnerLoopLatch,
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OuterLoopHeader, OuterLoopLatch, InnerLoop->getExitBlock());
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// For PHIs in the exit block of the outer loop, outer's latch has been
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// replaced by Inners'.
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OuterLoopLatchSuccessor->replacePhiUsesWith(OuterLoopLatch, InnerLoopLatch);
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@ -0,0 +1,181 @@
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; RUN: opt < %s -loop-interchange -loop-interchange-threshold=-100 -verify-loop-lcssa -S | FileCheck %s
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; Test case for PR41725. The induction variables in the latches escape the
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; loops and we must move some PHIs around.
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@a = common dso_local global i64 0, align 4
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@b = common dso_local global i64 0, align 4
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@c = common dso_local global [10 x [1 x i32 ]] zeroinitializer, align 16
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define void @test_lcssa_indvars1() {
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; CHECK-LABEL: @test_lcssa_indvars1()
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; CHECK-LABEL: inner.body.split:
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; CHECK-NEXT: %0 = phi i64 [ %iv.outer.next, %outer.latch ]
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; CHECK-NEXT: %iv.inner.next = add nsw i64 %iv.inner, -1
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; CHECK-LABEL: exit:
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; CHECK-NEXT: %v4.lcssa = phi i64 [ %0, %inner.body.split ]
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; CHECK-NEXT: %v8.lcssa.lcssa = phi i64 [ %iv.inner.next, %inner.body.split ]
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; CHECK-NEXT: store i64 %v8.lcssa.lcssa, i64* @b, align 4
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; CHECK-NEXT: store i64 %v4.lcssa, i64* @a, align 4
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entry:
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br label %outer.header
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outer.header: ; preds = %outer.latch, %entry
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%iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.latch ]
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br label %inner.body
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inner.body: ; preds = %inner.body, %outer.header
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%iv.inner = phi i64 [ 5, %outer.header ], [ %iv.inner.next, %inner.body ]
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%v7 = getelementptr inbounds [10 x [1 x i32]], [10 x [1 x i32]]* @c, i64 0, i64 %iv.inner, i64 %iv.outer
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store i32 0, i32* %v7, align 4
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%iv.inner.next = add nsw i64 %iv.inner, -1
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%v9 = icmp eq i64 %iv.inner, 0
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br i1 %v9, label %outer.latch, label %inner.body
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outer.latch: ; preds = %inner.body
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%v8.lcssa = phi i64 [ %iv.inner.next, %inner.body ]
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%iv.outer.next = add nuw nsw i64 %iv.outer, 1
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%v5 = icmp ult i64 %iv.outer, 2
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br i1 %v5, label %outer.header, label %exit
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exit: ; preds = %outer.latch
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%v4.lcssa = phi i64 [ %iv.outer.next, %outer.latch ]
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%v8.lcssa.lcssa = phi i64 [ %v8.lcssa, %outer.latch ]
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store i64 %v8.lcssa.lcssa, i64* @b, align 4
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store i64 %v4.lcssa, i64* @a, align 4
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ret void
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}
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define void @test_lcssa_indvars2() {
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; CHECK-LABEL: @test_lcssa_indvars2()
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; CHECK-LABEL: inner.body.split:
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; CHECK-NEXT: %0 = phi i64 [ %iv.outer, %outer.latch ]
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; CHECK-NEXT: %iv.inner.next = add nsw i64 %iv.inner, -1
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; CHECK-LABEL: exit:
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; CHECK-NEXT: %v4.lcssa = phi i64 [ %0, %inner.body.split ]
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; CHECK-NEXT: %v8.lcssa.lcssa = phi i64 [ %iv.inner, %inner.body.split ]
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; CHECK-NEXT: store i64 %v8.lcssa.lcssa, i64* @b, align 4
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; CHECK-NEXT: store i64 %v4.lcssa, i64* @a, align 4
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entry:
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br label %outer.header
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outer.header: ; preds = %outer.latch, %entry
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%iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.latch ]
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br label %inner.body
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inner.body: ; preds = %inner.body, %outer.header
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%iv.inner = phi i64 [ 5, %outer.header ], [ %iv.inner.next, %inner.body ]
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%v7 = getelementptr inbounds [10 x [1 x i32]], [10 x [1 x i32]]* @c, i64 0, i64 %iv.inner, i64 %iv.outer
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store i32 0, i32* %v7, align 4
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%iv.inner.next = add nsw i64 %iv.inner, -1
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%v9 = icmp eq i64 %iv.inner.next, 0
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br i1 %v9, label %outer.latch, label %inner.body
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outer.latch: ; preds = %inner.body
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%v8.lcssa = phi i64 [ %iv.inner, %inner.body ]
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%iv.outer.next = add nuw nsw i64 %iv.outer, 1
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%v5 = icmp ult i64 %iv.outer.next, 2
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br i1 %v5, label %outer.header, label %exit
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exit: ; preds = %outer.latch
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%v4.lcssa = phi i64 [ %iv.outer, %outer.latch ]
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%v8.lcssa.lcssa = phi i64 [ %v8.lcssa, %outer.latch ]
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store i64 %v8.lcssa.lcssa, i64* @b, align 4
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store i64 %v4.lcssa, i64* @a, align 4
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ret void
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}
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define void @test_lcssa_indvars3() {
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; CHECK-LABEL: @test_lcssa_indvars3()
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; CHECK-LABEL: inner.body.split:
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; CHECK-NEXT: %0 = phi i64 [ %iv.outer.next, %outer.latch ]
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; CHECK-NEXT: %iv.inner.next = add nsw i64 %iv.inner, -1
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; CHECK-LABEL: exit:
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; CHECK-NEXT: %v4.lcssa = phi i64 [ %0, %inner.body.split ]
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; CHECK-NEXT: %v8.lcssa.lcssa = phi i64 [ %iv.inner.next, %inner.body.split ]
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; CHECK-NEXT: %v8.lcssa.lcssa.2 = phi i64 [ %iv.inner.next, %inner.body.split ]
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; CHECK-NEXT: %r1 = add i64 %v8.lcssa.lcssa, %v8.lcssa.lcssa.2
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; CHECK-NEXT: store i64 %r1, i64* @b, align 4
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; CHECK-NEXT: store i64 %v4.lcssa, i64* @a, align 4
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entry:
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br label %outer.header
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outer.header: ; preds = %outer.latch, %entry
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%iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.latch ]
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br label %inner.body
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inner.body: ; preds = %inner.body, %outer.header
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%iv.inner = phi i64 [ 5, %outer.header ], [ %iv.inner.next, %inner.body ]
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%v7 = getelementptr inbounds [10 x [1 x i32]], [10 x [1 x i32]]* @c, i64 0, i64 %iv.inner, i64 %iv.outer
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store i32 0, i32* %v7, align 4
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%iv.inner.next = add nsw i64 %iv.inner, -1
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%v9 = icmp eq i64 %iv.inner, 0
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br i1 %v9, label %outer.latch, label %inner.body
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outer.latch: ; preds = %inner.body
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%v8.lcssa = phi i64 [ %iv.inner.next, %inner.body ]
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;%const.lcssa = phi i64 [ 111, %inner.body ]
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%iv.outer.next = add nuw nsw i64 %iv.outer, 1
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%v5 = icmp ult i64 %iv.outer, 2
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br i1 %v5, label %outer.header, label %exit
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exit: ; preds = %outer.latch
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%v4.lcssa = phi i64 [ %iv.outer.next, %outer.latch ]
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%v8.lcssa.lcssa = phi i64 [ %v8.lcssa, %outer.latch ]
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%v8.lcssa.lcssa.2 = phi i64 [ %v8.lcssa, %outer.latch ]
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%r1 = add i64 %v8.lcssa.lcssa, %v8.lcssa.lcssa.2
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store i64 %r1, i64* @b, align 4
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store i64 %v4.lcssa, i64* @a, align 4
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ret void
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}
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; Make sure we do not crash for loops without reachable exits.
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define void @no_reachable_exits() {
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; Check we interchanged.
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; CHECK-LABEL: @no_reachable_exits() {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label %inner.ph
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; CHECK-LABEL: outer.ph:
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; CHECK-NEXT: br label %outer.header
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; CHECK-LABEL: inner.ph:
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; CHECK-NEXT: br label %inner.body
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; CHECK-LABEL: inner.body:
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; CHECK-NEXT: %tmp31 = phi i32 [ 0, %inner.ph ], [ %tmp6, %inner.body.split ]
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; CHECK-NEXT: br label %outer.ph
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bb:
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br label %outer.ph
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outer.ph: ; preds = %bb
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br label %outer.header
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outer.header: ; preds = %outer.ph, %outer.latch
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%tmp2 = phi i32 [ 0, %outer.ph ], [ %tmp8, %outer.latch ]
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br i1 undef, label %inner.ph, label %outer.latch
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inner.ph: ; preds = %outer.header
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br label %inner.body
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inner.body: ; preds = %inner.ph, %inner.body
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%tmp31 = phi i32 [ 0, %inner.ph ], [ %tmp6, %inner.body]
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%tmp5 = load i32*, i32** undef, align 8
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%tmp6 = add nsw i32 %tmp31, 1
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br i1 undef, label %inner.body, label %outer.latch
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outer.latch: ; preds = %inner.body, %outer.header
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%tmp8 = add nsw i32 %tmp2, 1
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br i1 undef, label %outer.header, label %exit
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exit: ; preds = %outer.latch
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unreachable
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}
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