Trace copies when checking for rematerializability in spill weight calculation
PR24139 contains an analysis of poor register allocation. One of the findings was that when calculating the spill weight, a rematerializable interval once split is no longer rematerializable. This is because the isRematerializable check in CalcSpillWeights.cpp does not follow the copies introduced by live range splitting (after splitting, the live interval register definition is a copy which is not rematerializable). Reviewers: qcolombet Differential Revision: http://reviews.llvm.org/D11686 llvm-svn: 244439
This commit is contained in:
Robert Lougher
parent
a0e02410e1
commit
11a44b78a3
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@ -20,6 +20,7 @@ namespace llvm {
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class LiveIntervals;
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class MachineBlockFrequencyInfo;
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class MachineLoopInfo;
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class VirtRegMap;
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/// \brief Normalize the spill weight of a live interval
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///
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@ -51,6 +52,7 @@ namespace llvm {
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private:
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MachineFunction &MF;
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LiveIntervals &LIS;
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VirtRegMap *VRM;
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const MachineLoopInfo &Loops;
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const MachineBlockFrequencyInfo &MBFI;
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DenseMap<unsigned, float> Hint;
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@ -58,10 +60,10 @@ namespace llvm {
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public:
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VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
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const MachineLoopInfo &loops,
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VirtRegMap *vrm, const MachineLoopInfo &loops,
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const MachineBlockFrequencyInfo &mbfi,
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NormalizingFn norm = normalizeSpillWeight)
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: MF(mf), LIS(lis), Loops(loops), MBFI(mbfi), normalize(norm) {}
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: MF(mf), LIS(lis), VRM(vrm), Loops(loops), MBFI(mbfi), normalize(norm) {}
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/// \brief (re)compute li's spill weight and allocation hint.
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void calculateSpillWeightAndHint(LiveInterval &li);
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@ -70,6 +72,7 @@ namespace llvm {
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/// \brief Compute spill weights and allocation hints for all virtual register
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/// live intervals.
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void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF,
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VirtRegMap *VRM,
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const MachineLoopInfo &MLI,
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const MachineBlockFrequencyInfo &MBFI,
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VirtRegAuxInfo::NormalizingFn norm =
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@ -7,6 +7,7 @@
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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@ -24,6 +25,7 @@ using namespace llvm;
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void llvm::calculateSpillWeightsAndHints(LiveIntervals &LIS,
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MachineFunction &MF,
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VirtRegMap *VRM,
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const MachineLoopInfo &MLI,
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const MachineBlockFrequencyInfo &MBFI,
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VirtRegAuxInfo::NormalizingFn norm) {
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@ -31,7 +33,7 @@ void llvm::calculateSpillWeightsAndHints(LiveIntervals &LIS,
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<< "********** Function: " << MF.getName() << '\n');
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MachineRegisterInfo &MRI = MF.getRegInfo();
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VirtRegAuxInfo VRAI(MF, LIS, MLI, MBFI, norm);
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VirtRegAuxInfo VRAI(MF, LIS, VRM, MLI, MBFI, norm);
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for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (MRI.reg_nodbg_empty(Reg))
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@ -74,7 +76,10 @@ static unsigned copyHint(const MachineInstr *mi, unsigned reg,
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// Check if all values in LI are rematerializable
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static bool isRematerializable(const LiveInterval &LI,
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const LiveIntervals &LIS,
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VirtRegMap *VRM,
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const TargetInstrInfo &TII) {
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unsigned Reg = LI.reg;
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unsigned Original = VRM ? VRM->getOriginal(Reg) : 0;
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for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
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I != E; ++I) {
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const VNInfo *VNI = *I;
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@ -86,6 +91,36 @@ static bool isRematerializable(const LiveInterval &LI,
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MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
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assert(MI && "Dead valno in interval");
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// Trace copies introduced by live range splitting. The inline
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// spiller can rematerialize through these copies, so the spill
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// weight must reflect this.
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if (VRM) {
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while (MI->isFullCopy()) {
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// The copy destination must match the interval register.
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if (MI->getOperand(0).getReg() != Reg)
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return false;
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// Get the source register.
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Reg = MI->getOperand(1).getReg();
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// If the original (pre-splitting) registers match this
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// copy came from a split.
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if (!TargetRegisterInfo::isVirtualRegister(Reg) ||
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VRM->getOriginal(Reg) != Original)
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return false;
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// Follow the copy live-in value.
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const LiveInterval &SrcLI = LIS.getInterval(Reg);
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LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
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VNI = SrcQ.valueIn();
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assert(VNI && "Copy from non-existing value");
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if (VNI->isPHIDef())
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return false;
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MI = LIS.getInstructionFromIndex(VNI->def);
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assert(MI && "Dead valno in interval");
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}
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}
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if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis()))
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return false;
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}
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@ -188,7 +223,7 @@ VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &li) {
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// it is a preferred candidate for spilling.
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// FIXME: this gets much more complicated once we support non-trivial
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// re-materialization.
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if (isRematerializable(li, LIS, *MF.getSubtarget().getInstrInfo()))
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if (isRematerializable(li, LIS, VRM, *MF.getSubtarget().getInstrInfo()))
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totalWeight *= 0.5F;
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li.weight = normalize(totalWeight, li.getSize(), numInstr);
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@ -411,7 +411,7 @@ void
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LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
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const MachineLoopInfo &Loops,
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const MachineBlockFrequencyInfo &MBFI) {
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VirtRegAuxInfo VRAI(MF, LIS, Loops, MBFI);
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VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
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for (unsigned I = 0, Size = size(); I < Size; ++I) {
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LiveInterval &LI = LIS.getInterval(get(I));
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if (MRI.recomputeRegClass(LI.reg))
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@ -276,7 +276,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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getAnalysis<LiveIntervals>(),
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getAnalysis<LiveRegMatrix>());
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calculateSpillWeightsAndHints(*LIS, *MF,
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calculateSpillWeightsAndHints(*LIS, *MF, VRM,
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getAnalysis<MachineLoopInfo>(),
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getAnalysis<MachineBlockFrequencyInfo>());
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@ -2586,7 +2586,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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initializeCSRCost();
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calculateSpillWeightsAndHints(*LIS, mf, *Loops, *MBFI);
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calculateSpillWeightsAndHints(*LIS, mf, VRM, *Loops, *MBFI);
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DEBUG(LIS->dump());
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@ -724,11 +724,11 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
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MachineBlockFrequencyInfo &MBFI =
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getAnalysis<MachineBlockFrequencyInfo>();
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calculateSpillWeightsAndHints(LIS, MF, getAnalysis<MachineLoopInfo>(), MBFI,
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normalizePBQPSpillWeight);
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VirtRegMap &VRM = getAnalysis<VirtRegMap>();
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calculateSpillWeightsAndHints(LIS, MF, &VRM, getAnalysis<MachineLoopInfo>(),
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MBFI, normalizePBQPSpillWeight);
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std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
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MF.getRegInfo().freezeReservedRegs(MF);
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@ -0,0 +1,148 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
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; Check that we do not get excessive spilling from splitting of constant live ranges.
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; CHECK-LABEL: PR24139:
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; CHECK: # 16-byte Spill
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; CHECK-NOT: # 16-byte Spill
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; CHECK: retq
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define <2 x double> @PR24139(<2 x double> %arg, <2 x double> %arg1, <2 x double> %arg2) {
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%tmp = bitcast <2 x double> %arg to <4 x float>
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%tmp3 = fmul <4 x float> %tmp, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000>
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%tmp4 = bitcast <2 x double> %arg to <4 x i32>
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%tmp5 = and <4 x i32> %tmp4, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%tmp6 = or <4 x i32> %tmp5, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608>
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%tmp7 = bitcast <4 x i32> %tmp6 to <4 x float>
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%tmp8 = fadd <4 x float> %tmp3, %tmp7
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%tmp9 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp8) #2
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%tmp10 = bitcast <4 x i32> %tmp9 to <2 x i64>
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%tmp11 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp9) #2
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%tmp12 = fmul <4 x float> %tmp11, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000>
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%tmp13 = fsub <4 x float> %tmp, %tmp12
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%tmp14 = fmul <4 x float> %tmp11, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000>
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%tmp15 = fsub <4 x float> %tmp13, %tmp14
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%tmp16 = fmul <4 x float> %tmp15, %tmp15
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%tmp17 = fmul <4 x float> %tmp15, %tmp16
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%tmp18 = fmul <4 x float> %tmp16, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000>
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%tmp19 = fadd <4 x float> %tmp18, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000>
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%tmp20 = fmul <4 x float> %tmp16, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000>
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%tmp21 = fadd <4 x float> %tmp20, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000>
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%tmp22 = fmul <4 x float> %tmp16, %tmp19
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%tmp23 = fadd <4 x float> %tmp22, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000>
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%tmp24 = fmul <4 x float> %tmp16, %tmp21
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%tmp25 = fadd <4 x float> %tmp24, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000>
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%tmp26 = fmul <4 x float> %tmp16, %tmp23
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%tmp27 = fadd <4 x float> %tmp26, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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%tmp28 = fmul <4 x float> %tmp17, %tmp25
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%tmp29 = fadd <4 x float> %tmp15, %tmp28
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%tmp30 = and <2 x i64> %tmp10, <i64 4294967297, i64 4294967297>
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%tmp31 = bitcast <2 x i64> %tmp30 to <4 x i32>
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%tmp32 = icmp eq <4 x i32> %tmp31, zeroinitializer
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%tmp33 = sext <4 x i1> %tmp32 to <4 x i32>
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%tmp34 = bitcast <4 x i32> %tmp33 to <4 x float>
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%tmp35 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp27, <4 x float> %tmp29, <4 x float> %tmp34) #2
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%tmp36 = and <2 x i64> %tmp10, <i64 8589934594, i64 8589934594>
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%tmp37 = bitcast <2 x i64> %tmp36 to <4 x i32>
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%tmp38 = icmp eq <4 x i32> %tmp37, zeroinitializer
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%tmp39 = sext <4 x i1> %tmp38 to <4 x i32>
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%tmp40 = bitcast <4 x float> %tmp35 to <4 x i32>
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%tmp41 = xor <4 x i32> %tmp40, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%tmp42 = bitcast <4 x i32> %tmp41 to <4 x float>
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%tmp43 = bitcast <4 x i32> %tmp39 to <4 x float>
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%tmp44 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp42, <4 x float> %tmp35, <4 x float> %tmp43) #2
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%tmp45 = bitcast <2 x double> %arg1 to <4 x float>
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%tmp46 = fmul <4 x float> %tmp45, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000>
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%tmp47 = bitcast <2 x double> %arg1 to <4 x i32>
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%tmp48 = and <4 x i32> %tmp47, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%tmp49 = or <4 x i32> %tmp48, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608>
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%tmp50 = bitcast <4 x i32> %tmp49 to <4 x float>
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%tmp51 = fadd <4 x float> %tmp46, %tmp50
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%tmp52 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp51) #2
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%tmp53 = bitcast <4 x i32> %tmp52 to <2 x i64>
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%tmp54 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp52) #2
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%tmp55 = fmul <4 x float> %tmp54, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000>
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%tmp56 = fsub <4 x float> %tmp45, %tmp55
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%tmp57 = fmul <4 x float> %tmp54, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000>
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%tmp58 = fsub <4 x float> %tmp56, %tmp57
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%tmp59 = fmul <4 x float> %tmp58, %tmp58
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%tmp60 = fmul <4 x float> %tmp58, %tmp59
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%tmp61 = fmul <4 x float> %tmp59, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000>
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%tmp62 = fadd <4 x float> %tmp61, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000>
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%tmp63 = fmul <4 x float> %tmp59, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000>
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%tmp64 = fadd <4 x float> %tmp63, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000>
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%tmp65 = fmul <4 x float> %tmp59, %tmp62
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%tmp66 = fadd <4 x float> %tmp65, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000>
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%tmp67 = fmul <4 x float> %tmp59, %tmp64
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%tmp68 = fadd <4 x float> %tmp67, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000>
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%tmp69 = fmul <4 x float> %tmp59, %tmp66
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%tmp70 = fadd <4 x float> %tmp69, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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%tmp71 = fmul <4 x float> %tmp60, %tmp68
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%tmp72 = fadd <4 x float> %tmp58, %tmp71
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%tmp73 = and <2 x i64> %tmp53, <i64 4294967297, i64 4294967297>
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%tmp74 = bitcast <2 x i64> %tmp73 to <4 x i32>
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%tmp75 = icmp eq <4 x i32> %tmp74, zeroinitializer
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%tmp76 = sext <4 x i1> %tmp75 to <4 x i32>
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%tmp77 = bitcast <4 x i32> %tmp76 to <4 x float>
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%tmp78 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp70, <4 x float> %tmp72, <4 x float> %tmp77) #2
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%tmp79 = and <2 x i64> %tmp53, <i64 8589934594, i64 8589934594>
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%tmp80 = bitcast <2 x i64> %tmp79 to <4 x i32>
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%tmp81 = icmp eq <4 x i32> %tmp80, zeroinitializer
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%tmp82 = sext <4 x i1> %tmp81 to <4 x i32>
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%tmp83 = bitcast <4 x float> %tmp78 to <4 x i32>
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%tmp84 = xor <4 x i32> %tmp83, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%tmp85 = bitcast <4 x i32> %tmp84 to <4 x float>
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%tmp86 = bitcast <4 x i32> %tmp82 to <4 x float>
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%tmp87 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp85, <4 x float> %tmp78, <4 x float> %tmp86) #2
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%tmp88 = fadd <4 x float> %tmp44, %tmp87
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%tmp89 = bitcast <2 x double> %arg2 to <4 x float>
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%tmp90 = fmul <4 x float> %tmp89, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000>
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%tmp91 = bitcast <2 x double> %arg2 to <4 x i32>
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%tmp92 = and <4 x i32> %tmp91, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%tmp93 = or <4 x i32> %tmp92, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608>
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%tmp94 = bitcast <4 x i32> %tmp93 to <4 x float>
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%tmp95 = fadd <4 x float> %tmp90, %tmp94
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%tmp96 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp95) #2
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%tmp97 = bitcast <4 x i32> %tmp96 to <2 x i64>
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%tmp98 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp96) #2
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%tmp99 = fmul <4 x float> %tmp98, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000>
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%tmp100 = fsub <4 x float> %tmp89, %tmp99
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%tmp101 = fmul <4 x float> %tmp98, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000>
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%tmp102 = fsub <4 x float> %tmp100, %tmp101
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%tmp103 = fmul <4 x float> %tmp102, %tmp102
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%tmp104 = fmul <4 x float> %tmp102, %tmp103
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%tmp105 = fmul <4 x float> %tmp103, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000>
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%tmp106 = fadd <4 x float> %tmp105, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000>
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%tmp107 = fmul <4 x float> %tmp103, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000>
|
||||
%tmp108 = fadd <4 x float> %tmp107, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000>
|
||||
%tmp109 = fmul <4 x float> %tmp103, %tmp106
|
||||
%tmp110 = fadd <4 x float> %tmp109, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000>
|
||||
%tmp111 = fmul <4 x float> %tmp103, %tmp108
|
||||
%tmp112 = fadd <4 x float> %tmp111, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000>
|
||||
%tmp113 = fmul <4 x float> %tmp103, %tmp110
|
||||
%tmp114 = fadd <4 x float> %tmp113, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
|
||||
%tmp115 = fmul <4 x float> %tmp104, %tmp112
|
||||
%tmp116 = fadd <4 x float> %tmp102, %tmp115
|
||||
%tmp117 = and <2 x i64> %tmp97, <i64 4294967297, i64 4294967297>
|
||||
%tmp118 = bitcast <2 x i64> %tmp117 to <4 x i32>
|
||||
%tmp119 = icmp eq <4 x i32> %tmp118, zeroinitializer
|
||||
%tmp120 = sext <4 x i1> %tmp119 to <4 x i32>
|
||||
%tmp121 = bitcast <4 x i32> %tmp120 to <4 x float>
|
||||
%tmp122 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp114, <4 x float> %tmp116, <4 x float> %tmp121) #2
|
||||
%tmp123 = and <2 x i64> %tmp97, <i64 8589934594, i64 8589934594>
|
||||
%tmp124 = bitcast <2 x i64> %tmp123 to <4 x i32>
|
||||
%tmp125 = icmp eq <4 x i32> %tmp124, zeroinitializer
|
||||
%tmp126 = sext <4 x i1> %tmp125 to <4 x i32>
|
||||
%tmp127 = bitcast <4 x float> %tmp122 to <4 x i32>
|
||||
%tmp128 = xor <4 x i32> %tmp127, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
|
||||
%tmp129 = bitcast <4 x i32> %tmp128 to <4 x float>
|
||||
%tmp130 = bitcast <4 x i32> %tmp126 to <4 x float>
|
||||
%tmp131 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp129, <4 x float> %tmp122, <4 x float> %tmp130) #2
|
||||
%tmp132 = fadd <4 x float> %tmp88, %tmp131
|
||||
%tmp133 = bitcast <4 x float> %tmp132 to <2 x double>
|
||||
ret <2 x double> %tmp133
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>)
|
||||
declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>)
|
||||
declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>)
|
||||
Loading…
Reference in New Issue