From 10fc3cfc637695cb1d4ec946a2327c886859b996 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Wed, 23 Nov 2016 15:51:52 +0000 Subject: [PATCH] [PowerPC] Remove InstAlias definitions that cause incorrect assembly In rL283190, I added some InstAlias definitions to generate extended mnemonics for some uses of the XXPERMDI instruction. However, when the assembler matches these extended mnemonics, it matches the new instruction in situations where it should match the old one. This patch removes these definitions and accomplishes that by defining these mnemonics with additional instructions that are isCodeGenOnly. Fixes PR31127. llvm-svn: 287765 --- llvm/lib/Target/PowerPC/PPCInstrVSX.td | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index c9bd16977ec9..daf22a13c444 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -821,9 +821,19 @@ let Uses = [RM] in { def XXPERMDI : XX3Form_2<60, 10, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM), "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, []>; - let isCodeGenOnly = 1 in + let isCodeGenOnly = 1 in { def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vfrc:$XA, u2imm:$DM), "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>; + let D = 0 in + def XXSPLTD0s : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vfrc:$XA), + "xxspltd $XT, $XA, 0", IIC_VecPerm, []>; + let D = 1 in + def XXSPLTD1s : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vfrc:$XA), + "xxspltd $XT, $XA, 1", IIC_VecPerm, []>; + let D = 2 in + def XXSWAPDs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vfrc:$XA), + "xxswapd $XT, $XA", IIC_VecPerm, []>; + } def XXSEL : XX4Form<60, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC), "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>; @@ -895,12 +905,6 @@ def : InstAlias<"xxmrgld $XT, $XA, $XB", (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>; def : InstAlias<"xxswapd $XT, $XB", (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>; -def : InstAlias<"xxspltd $XT, $XB, 0", - (XXPERMDIs vsrc:$XT, vfrc:$XB, 0)>; -def : InstAlias<"xxspltd $XT, $XB, 1", - (XXPERMDIs vsrc:$XT, vfrc:$XB, 3)>; -def : InstAlias<"xxswapd $XT, $XB", - (XXPERMDIs vsrc:$XT, vfrc:$XB, 2)>; let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns. @@ -2496,11 +2500,11 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { def : Pat<(v4i32 (scalar_to_vector ScalarLoads.ZELi8)), (v4i32 (XXSPLTWs (LXSIBZX xoaddr:$src), 1))>; def : Pat<(v2i64 (scalar_to_vector ScalarLoads.ZELi8i64)), - (v2i64 (XXPERMDIs (LXSIBZX xoaddr:$src), 0))>; + (v2i64 (XXSPLTD0s (LXSIBZX xoaddr:$src)))>; def : Pat<(v4i32 (scalar_to_vector ScalarLoads.SELi8)), (v4i32 (XXSPLTWs (VEXTSB2Ws (LXSIBZX xoaddr:$src)), 1))>; def : Pat<(v2i64 (scalar_to_vector ScalarLoads.SELi8i64)), - (v2i64 (XXPERMDIs (VEXTSB2Ds (LXSIBZX xoaddr:$src)), 0))>; + (v2i64 (XXSPLTD0s (VEXTSB2Ds (LXSIBZX xoaddr:$src))))>; // Build vectors from i16 loads def : Pat<(v8i16 (scalar_to_vector ScalarLoads.Li16)), @@ -2508,11 +2512,11 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { def : Pat<(v4i32 (scalar_to_vector ScalarLoads.ZELi16)), (v4i32 (XXSPLTWs (LXSIHZX xoaddr:$src), 1))>; def : Pat<(v2i64 (scalar_to_vector ScalarLoads.ZELi16i64)), - (v2i64 (XXPERMDIs (LXSIHZX xoaddr:$src), 0))>; + (v2i64 (XXSPLTD0s (LXSIHZX xoaddr:$src)))>; def : Pat<(v4i32 (scalar_to_vector ScalarLoads.SELi16)), (v4i32 (XXSPLTWs (VEXTSH2Ws (LXSIHZX xoaddr:$src)), 1))>; def : Pat<(v2i64 (scalar_to_vector ScalarLoads.SELi16i64)), - (v2i64 (XXPERMDIs (VEXTSH2Ds (LXSIHZX xoaddr:$src)), 0))>; + (v2i64 (XXSPLTD0s (VEXTSH2Ds (LXSIHZX xoaddr:$src))))>; let Predicates = [IsBigEndian, HasP9Vector] in { // Scalar stores of i8