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Use the source-order scheduler instead of the "fast" scheduler at -O0, 

because it's more likely to keep debug line information in its original
order.

llvm-svn: 108496
This commit is contained in:
Dan Gohman 2010-07-16 02:01:19 +00:00
parent bdb298912b
commit 103c4ebea5
3 changed files with 4 additions and 4 deletions
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2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -132,7 +132,7 @@ namespace llvm {
const TargetLowering &TLI = IS->getTargetLowering();
if (OptLevel == CodeGenOpt::None)
return createFastDAGScheduler(IS, OptLevel);
return createSourceListDAGScheduler(IS, OptLevel);
if (TLI.getSchedulingPreference() == Sched::Latency)
return createTDListDAGScheduler(IS, OptLevel);
if (TLI.getSchedulingPreference() == Sched::RegPressure)

4
llvm/test/CodeGen/X86/fast-isel-gep.ll
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@ -9,7 +9,7 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind {
%t15 = load i32* %t9 ; <i32> [#uses=1]
ret i32 %t15
; X32: test1:
; X32: movl (%ecx,%eax,4), %eax
; X32: movl (%eax,%ecx,4), %eax
; X32: ret
; X64: test1:
@ -23,7 +23,7 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind {
%t15 = load i32* %t9 ; <i32> [#uses=1]
ret i32 %t15
; X32: test2:
; X32: movl (%eax,%ecx,4), %eax
; X32: movl (%edx,%ecx,4), %eax
; X32: ret
; X64: test2:

2
llvm/test/CodeGen/X86/fast-isel-shift-imm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %eax}
; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %e}
; PR3242
define void @foo(i32 %x, i32* %p) nounwind {