Add a MinNumRegs argument to MRI::constrainRegClass().
The function will refuse to use a register class with fewer registers than MinNumRegs. This can be used by clients to avoid accidentally increase register pressure too much. The default value of MinNumRegs=0 doesn't affect how constrainRegClass() works. llvm-svn: 140339
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@ -215,13 +215,15 @@ public:
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void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
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/// constrainRegClass - Constrain the register class of the specified virtual
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/// register to be a common subclass of RC and the current register class.
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/// Return the new register class, or NULL if no such class exists.
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/// register to be a common subclass of RC and the current register class,
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/// but only if the new class has at least MinNumRegs registers. Return the
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/// new register class, or NULL if no such class exists.
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/// This should only be used when the constraint is known to be trivial, like
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/// GR32 -> GR32_NOSP. Beware of increasing register pressure.
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///
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const TargetRegisterClass *constrainRegClass(unsigned Reg,
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const TargetRegisterClass *RC);
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const TargetRegisterClass *RC,
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unsigned MinNumRegs = 0);
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/// recomputeRegClass - Try to find a legal super-class of Reg's register
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/// class that still satisfies the constraints from the instructions using
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@ -49,14 +49,16 @@ MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
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const TargetRegisterClass *
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MachineRegisterInfo::constrainRegClass(unsigned Reg,
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const TargetRegisterClass *RC) {
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const TargetRegisterClass *RC,
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unsigned MinNumRegs) {
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const TargetRegisterClass *OldRC = getRegClass(Reg);
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if (OldRC == RC)
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return RC;
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const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
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if (!NewRC)
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if (!NewRC || NewRC == OldRC)
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return NewRC;
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if (NewRC->getNumRegs() < MinNumRegs)
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return 0;
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if (NewRC != OldRC)
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setRegClass(Reg, NewRC);
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return NewRC;
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}
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