Add a MinNumRegs argument to MRI::constrainRegClass().

The function will refuse to use a register class with fewer registers
than MinNumRegs.  This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

llvm-svn: 140339
This commit is contained in:
Jakob Stoklund Olesen 2011-09-22 21:39:31 +00:00
parent 16abd328f5
commit 0f36544c08
2 changed files with 11 additions and 7 deletions

View File

@ -215,13 +215,15 @@ public:
void setRegClass(unsigned Reg, const TargetRegisterClass *RC); void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
/// constrainRegClass - Constrain the register class of the specified virtual /// constrainRegClass - Constrain the register class of the specified virtual
/// register to be a common subclass of RC and the current register class. /// register to be a common subclass of RC and the current register class,
/// Return the new register class, or NULL if no such class exists. /// but only if the new class has at least MinNumRegs registers. Return the
/// new register class, or NULL if no such class exists.
/// This should only be used when the constraint is known to be trivial, like /// This should only be used when the constraint is known to be trivial, like
/// GR32 -> GR32_NOSP. Beware of increasing register pressure. /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
/// ///
const TargetRegisterClass *constrainRegClass(unsigned Reg, const TargetRegisterClass *constrainRegClass(unsigned Reg,
const TargetRegisterClass *RC); const TargetRegisterClass *RC,
unsigned MinNumRegs = 0);
/// recomputeRegClass - Try to find a legal super-class of Reg's register /// recomputeRegClass - Try to find a legal super-class of Reg's register
/// class that still satisfies the constraints from the instructions using /// class that still satisfies the constraints from the instructions using

View File

@ -49,15 +49,17 @@ MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
const TargetRegisterClass * const TargetRegisterClass *
MachineRegisterInfo::constrainRegClass(unsigned Reg, MachineRegisterInfo::constrainRegClass(unsigned Reg,
const TargetRegisterClass *RC) { const TargetRegisterClass *RC,
unsigned MinNumRegs) {
const TargetRegisterClass *OldRC = getRegClass(Reg); const TargetRegisterClass *OldRC = getRegClass(Reg);
if (OldRC == RC) if (OldRC == RC)
return RC; return RC;
const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC); const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
if (!NewRC) if (!NewRC || NewRC == OldRC)
return NewRC;
if (NewRC->getNumRegs() < MinNumRegs)
return 0; return 0;
if (NewRC != OldRC) setRegClass(Reg, NewRC);
setRegClass(Reg, NewRC);
return NewRC; return NewRC;
} }