Revert "Strip metadata when speculatively hoisting instructions"
This reverts commit r252604, as it broke all ARM and AArch64 buildbots, as well as some x86, et al. llvm-svn: 252623
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@ -120,13 +120,6 @@ bool Loop::makeLoopInvariant(Instruction *I, bool &Changed,
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// Hoist.
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// Hoist.
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I->moveBefore(InsertPt);
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I->moveBefore(InsertPt);
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// There is possibility of hoisting this instruction above some arbitrary
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// condition. Any metadata defined on it can be control dependent on this
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// condition. Conservatively strip it here so that we don't give any wrong
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// information to the optimizer.
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I->dropUnknownNonDebugMetadata();
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Changed = true;
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Changed = true;
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return true;
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return true;
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}
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}
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@ -672,10 +672,6 @@ static bool hoist(Instruction &I, BasicBlock *Preheader) {
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// Move the new node to the Preheader, before its terminator.
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// Move the new node to the Preheader, before its terminator.
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I.moveBefore(Preheader->getTerminator());
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I.moveBefore(Preheader->getTerminator());
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// Metadata can be dependent on the condition we are hoisting above.
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// Conservatively strip all metadata on the instruction.
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I.dropUnknownNonDebugMetadata();
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if (isa<LoadInst>(I)) ++NumMovedLoads;
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if (isa<LoadInst>(I)) ++NumMovedLoads;
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else if (isa<CallInst>(I)) ++NumMovedCalls;
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else if (isa<CallInst>(I)) ++NumMovedCalls;
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++NumHoisted;
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++NumHoisted;
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@ -1618,11 +1618,6 @@ static bool SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *ThenBB,
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SpeculatedStore->setOperand(0, S);
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SpeculatedStore->setOperand(0, S);
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}
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}
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// Metadata can be dependent on the condition we are hoisting above.
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// Conservatively strip all metadata on the instruction.
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for (auto &I: *ThenBB)
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I.dropUnknownNonDebugMetadata();
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// Hoist the instructions.
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// Hoist the instructions.
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BB->getInstList().splice(BI->getIterator(), ThenBB->getInstList(),
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BB->getInstList().splice(BI->getIterator(), ThenBB->getInstList(),
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ThenBB->begin(), std::prev(ThenBB->end()));
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ThenBB->begin(), std::prev(ThenBB->end()));
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@ -5,7 +5,7 @@
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; CHECK: @foo
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; CHECK: @foo
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; CHECK: entry:
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; CHECK: entry:
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; CHECK-NEXT: %tmp3 = load double*, double** @P
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; CHECK-NEXT: %tmp3 = load double*, double** @P, !tbaa !0
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; CHECK-NEXT: br label %for.body
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; CHECK-NEXT: br label %for.body
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@P = common global double* null
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@P = common global double* null
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@ -388,49 +388,5 @@ for.end: ; preds = %for.inc, %entry
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ret void
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ret void
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}
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}
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; In this test we should be able to only hoist load from %cptr. We can't hoist
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; load from %c because it's dereferenceability can depend on %cmp1 condition.
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; By moving it out of the loop we break this dependency and can not rely
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; on the dereferenceability anymore.
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; In other words this test checks that we strip dereferenceability metadata
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; after hoisting an instruction.
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; CHECK-LABEL: @test10
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; CHECK: %c = load i32*, i32** %cptr
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; CHECK-NOT: dereferenceable
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; CHECK: if.then:
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; CHECK: load i32, i32* %c, align 4
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define void @test10(i32* noalias %a, i32* %b, i32** dereferenceable(8) %cptr, i32 %n) #0 {
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entry:
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%cmp11 = icmp sgt i32 %n, 0
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br i1 %cmp11, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.inc
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4
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%cmp1 = icmp sgt i32 %0, 0
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br i1 %cmp1, label %if.then, label %for.inc
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if.then: ; preds = %for.body
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%c = load i32*, i32** %cptr, !dereferenceable !0
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%1 = load i32, i32* %c, align 4
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%arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
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%2 = load i32, i32* %arrayidx3, align 4
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%mul = mul nsw i32 %2, %1
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store i32 %mul, i32* %arrayidx, align 4
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.inc, %entry
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ret void
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}
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attributes #0 = { nounwind uwtable }
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attributes #0 = { nounwind uwtable }
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!0 = !{i64 4}
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!0 = !{i64 4}
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@ -69,29 +69,3 @@ end:
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ret i8* %x10
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ret i8* %x10
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}
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}
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define i32* @test5(i32 %a, i32 %b, i32 %c, i32* dereferenceable(10) %ptr1,
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i32* dereferenceable(10) %ptr2, i32** dereferenceable(10) %ptr3) nounwind {
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; CHECK-LABEL: @test5(
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entry:
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%tmp1 = icmp eq i32 %b, 0
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br i1 %tmp1, label %bb1, label %bb3
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bb1: ; preds = %entry
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%tmp2 = icmp sgt i32 %c, 1
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br i1 %tmp2, label %bb2, label %bb3
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; CHECK: bb1:
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; CHECK-NEXT: icmp sgt i32 %c, 1
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; CHECK-NEXT: load i32*, i32** %ptr3
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; CHECK-NOT: dereferenceable
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; CHECK-NEXT: select i1 %tmp2, i32* %tmp3, i32* %ptr2
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; CHECK-NEXT: ret i32* %tmp3.ptr2
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bb2: ; preds = bb1
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%tmp3 = load i32*, i32** %ptr3, !dereferenceable !{i64 10}
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br label %bb3
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bb3: ; preds = %bb2, %entry
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%tmp4 = phi i32* [ %ptr1, %entry ], [ %ptr2, %bb1 ], [ %tmp3, %bb2 ]
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ret i32* %tmp4
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}
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