[ARM] Allow zext in ARMCodeGenPrepare
Treat zext instructions as roots, like we do for truncs. Differential Revision: https://reviews.llvm.org/D50759 llvm-svn: 339868
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@ -181,6 +181,8 @@ static bool isSink(Value *V) {
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return UsesNarrowValue(Return->getReturnValue());
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if (auto *Trunc = dyn_cast<TruncInst>(V))
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return UsesNarrowValue(Trunc->getOperand(0));
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if (auto *ZExt = dyn_cast<ZExtInst>(V))
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return UsesNarrowValue(ZExt->getOperand(0));
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if (auto *ICmp = dyn_cast<ICmpInst>(V))
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return ICmp->isSigned();
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@ -422,7 +424,8 @@ void IRPromoter::Mutate(Type *OrigTy,
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if (!isa<Instruction>(V) || !isa<IntegerType>(V->getType()))
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return nullptr;
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if ((!Promoted.count(V) && !NewInsts.count(V)) || !TruncTysMap.count(V))
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if ((!Promoted.count(V) && !NewInsts.count(V)) || !TruncTysMap.count(V) ||
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Leaves.count(V))
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return nullptr;
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Type *TruncTy = TruncTysMap[V];
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@ -463,7 +466,7 @@ void IRPromoter::Mutate(Type *OrigTy,
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}
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}
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}
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LLVM_DEBUG(dbgs() << "ARM CGP: Mutation complete.\n");
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LLVM_DEBUG(dbgs() << "ARM CGP: Mutation complete:\n");
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}
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/// We accept most instructions, as well as Arguments and ConstantInsts. We
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@ -492,10 +495,12 @@ bool ARMCodeGenPrepare::isSupportedValue(Value *V) {
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isa<LoadInst>(V))
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return isSupportedType(V);
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// Currently, Trunc is the only cast we support.
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if (auto *Trunc = dyn_cast<TruncInst>(V))
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return isSupportedType(Trunc->getOperand(0));
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if (auto *ZExt = dyn_cast<ZExtInst>(V))
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return isSupportedType(ZExt->getOperand(0));
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// Special cases for calls as we need to check for zeroext
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// TODO We should accept calls even if they don't have zeroext, as they can
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// still be roots.
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@ -42,7 +42,7 @@ define i16 @promote_i8_sink_i16_1(i8 zeroext %arg0, i16 zeroext %arg1, i16 zeroe
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; CHECK-COMMON-LABEL: promote_i8_sink_i16_2
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; CHECK-COMMON: bl dummy_i8
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; CHECK-COMMON: adds r0, #1
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; CHECK-COMMON: uxtb r0, r0
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; CHECK-COMMON-NOT: uxt
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; CHECK-COMMON: cmp r0
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define i16 @promote_i8_sink_i16_2(i8 zeroext %arg0, i8 zeroext %arg1, i16 zeroext %arg2) {
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%call = tail call zeroext i8 @dummy_i8(i8 %arg0)
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@ -51,12 +51,12 @@ entry:
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ret i8 %4
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}
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; The pass will bail because of the zext, otherwise we'd want something like:
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; ldrb [[LD:r[^ ]+]], [r0]
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; subs [[SUB:r[^ ]+]], [[LD]], #1
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; cmp [[LD]], [[SUB]]
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; The pass perform the transform, but a uxtb will still be inserted to handle
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; the zext to the icmp.
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; CHECK-COMMON-LABEL: icmp_i32_zext:
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; CHECK-COMMON: sub
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; CHECK-COMMON: uxtb
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; CHECK-COMMON: cmp
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define i8 @icmp_i32_zext(i8* %ptr) {
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entry:
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%gep = getelementptr inbounds i8, i8* %ptr, i32 0
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@ -85,8 +85,10 @@ exit:
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ret i8 %2
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}
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; Won't handle zext or sext
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; Won't don't handle sext
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; CHECK-COMMON-LABEL: icmp_sext_zext_store_i8_i16
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; CHECK-COMMON: ldrb
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; CHECK-COMMON: ldrsh
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define i32 @icmp_sext_zext_store_i8_i16() {
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entry:
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%0 = load i8, i8* getelementptr inbounds ([16 x i8], [16 x i8]* @d_uch, i32 0, i32 2), align 1
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@ -100,12 +102,13 @@ entry:
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ret i32 %conv3
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}
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; Pass will bail because of the zext, otherwise:
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; ldrb [[LD:r[^ ]+]], [r1]
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; subs [[SUB:r[^ ]+]], #1
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; cmp [[SUB]], #3
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; CHECK-COMMON-LABEL: or_icmp_ugt:
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; CHECK-COMMON: uxt
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; CHECK-COMMON: ldrb
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; CHECK-COMMON: sub.w
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; CHECK-COMMON-NOT: uxt
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; CHECK-COMMON: cmp.w
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; CHECK-COMMON-NOT: uxt
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; CHECK-COMMON: cmp
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define i1 @or_icmp_ugt(i32 %arg, i8* %ptr) {
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entry:
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%0 = load i8, i8* %ptr
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@ -149,9 +152,12 @@ exit:
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ret i16 %res
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}
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; Pass will bail because of the zext
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; We currently only handle truncs as sinks, so a uxt will still be needed for
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; the icmp ugt instruction.
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; CHECK-COMMON-LABEL: urem_trunc_icmps
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; CHECK-COMMON: cmp
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; CHECK-COMMON: uxt
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; CHECK-COMMON: cmp
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define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) {
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entry:
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%ptr = load i16*, i16** %in, align 4
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@ -223,7 +229,6 @@ exit:
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ret void
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}
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; Again, zexts will prevent the transform.
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; Check that %exp requires uxth in all cases, and will also be required to
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; promote %1 for the call - unless we can generate a uadd16.
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; CHECK-COMMON-LABEL: zext_load_sink_call:
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