diff --git a/llvm/lib/Target/ARM64/ARM64InstrInfo.cpp b/llvm/lib/Target/ARM64/ARM64InstrInfo.cpp
index 75d906d9da0f..e4112655f8db 100644
--- a/llvm/lib/Target/ARM64/ARM64InstrInfo.cpp
+++ b/llvm/lib/Target/ARM64/ARM64InstrInfo.cpp
@@ -827,14 +827,11 @@ bool ARM64InstrInfo::optimizeCompareInstr(
 
 /// Return true if this is this instruction has a non-zero immediate
 bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const {
-  switch (MI->getOpcode()) {
-  default:
-    if (MI->getOperand(3).isImm()) {
-      unsigned val = MI->getOperand(3).getImm();
-      return (val != 0);
-    }
-    break;
+  if (MI->getOperand(3).isImm()) {
+    unsigned val = MI->getOperand(3).getImm();
+    return (val != 0);
   }
+
   return false;
 }
 
diff --git a/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp b/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp
index 66d107432163..b759495ad8e2 100644
--- a/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp
@@ -37,10 +37,8 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
 { }
 
 enum AMDGPUMCInstLower::SISubtarget
-AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
-  switch (Gen) {
-  default: return AMDGPUMCInstLower::SI;
-  }
+AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const {
+  return AMDGPUMCInstLower::SI;
 }
 
 unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {