[AArch64][FastISel] Variant of the logical instructions that use two input
registers cannot write on SP. rdar://problem/20748715 llvm-svn: 236352
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@ -2573,7 +2573,7 @@ bool AArch64FastISel::optimizeSelect(const SelectInst *SI) {
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Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1);
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Src1IsKill = true;
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}
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unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32spRegClass, Src1Reg,
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unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
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Src1IsKill, Src2Reg, Src2IsKill);
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updateValueMap(SI, ResultReg);
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return true;
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@ -114,3 +114,22 @@ entry:
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}
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declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
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define void @logicalReg() {
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; Make sure we generate a logical reg = reg, reg instruction without any
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; machine verifier errors.
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; CHECK-LABEL: logicalReg:
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; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
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; CHECK: ret
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entry:
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br i1 undef, label %cond.end, label %cond.false
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cond.false:
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%cond = select i1 undef, i1 true, i1 false
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br label %cond.end
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cond.end:
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%cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
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ret void
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}
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