[x86] Add a slight variation on some of the other generic shuffle
lowerings -- one which decomposes into an initial blend followed by a permute. Particularly on newer chips, blends are handled independently of shuffles and so this is much less bottlenecked on the single port that floating point shuffles are executed with on Intel. I'll be adding this lowering to a bunch of other code paths in subsequent commits to handle still more places where we can effectively leverage blends when they're available in the ISA. llvm-svn: 229292
This commit is contained in:
Chandler Carruth
parent
0c691d029a
commit
0ddfe0c7c5
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@ -7543,6 +7543,38 @@ static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
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}
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}
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/// \brief Try to lower as a blend of elements from two inputs followed by
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/// a single-input permutation.
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///
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/// This matches the pattern where we can blend elements from two inputs and
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/// then reduce the shuffle to a single-input permutation.
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static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
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SDValue V2,
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ArrayRef<int> Mask,
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SelectionDAG &DAG) {
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// We build up the blend mask while checking whether a blend is a viable way
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// to reduce the shuffle.
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SmallVector<int, 32> BlendMask(Mask.size(), -1);
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SmallVector<int, 32> PermuteMask(Mask.size(), -1);
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for (int i = 0, Size = Mask.size(); i < Size; ++i) {
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if (Mask[i] < 0)
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continue;
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assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
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if (BlendMask[Mask[i] % Size] == -1)
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BlendMask[Mask[i] % Size] = Mask[i];
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else if (BlendMask[Mask[i] % Size] != Mask[i])
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return SDValue(); // Can't blend in the needed input!
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PermuteMask[i] = Mask[i] % Size;
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}
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SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
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return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
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}
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/// \brief Generic routine to lower a shuffle and blend as a decomposed set of
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/// unblended shuffles followed by an unshuffled blend.
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///
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@ -8552,6 +8584,24 @@ static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
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}
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/// \brief Test whether this can be lowered with a single SHUFPS instruction.
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///
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/// This is used to disable more specialized lowerings when the shufps lowering
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/// will happen to be efficient.
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static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
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// This routine only handles 128-bit shufps.
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assert(Mask.size() == 4 && "Unsupported mask size!");
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// To lower with a single SHUFPS we need to have the low half and high half
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// each requiring a single input.
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if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4 != Mask[1] < 4))
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return false;
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if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4 != Mask[3] < 4))
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return false;
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return true;
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}
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/// \brief Lower a vector shuffle using the SHUFPS instruction.
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///
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/// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
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@ -8712,6 +8762,11 @@ static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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// Use INSERTPS if we can complete the shuffle efficiently.
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if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
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return V;
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if (!isSingleSHUFPSMask(Mask))
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if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
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DL, MVT::v4f32, V1, V2, Mask, DAG))
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return BlendPerm;
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}
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// Otherwise fall back to a SHUFPS lowering strategy.
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@ -295,11 +295,11 @@ define <8 x float> @shuffle_v8f32_08192a3b(<8 x float> %a, <8 x float> %b) {
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define <8 x float> @shuffle_v8f32_08991abb(<8 x float> %a, <8 x float> %b) {
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; AVX1-LABEL: shuffle_v8f32_08991abb:
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; AVX1: # BB#0:
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[1,0],xmm1[2,0]
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[3,3]
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; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
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; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,0],xmm1[0,0]
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1]
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; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: shuffle_v8f32_08991abb:
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@ -1133,11 +1133,11 @@ define <8 x i32> @shuffle_v8i32_08192a3b(<8 x i32> %a, <8 x i32> %b) {
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define <8 x i32> @shuffle_v8i32_08991abb(<8 x i32> %a, <8 x i32> %b) {
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; AVX1-LABEL: shuffle_v8i32_08991abb:
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; AVX1: # BB#0:
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[1,0],xmm1[2,0]
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[3,3]
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; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
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; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,0],xmm1[0,0]
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1]
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; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: shuffle_v8i32_08991abb:
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@ -875,16 +875,28 @@ define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
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}
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define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
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; SSE-LABEL: combine_nested_undef_test16:
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,3]
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSE-NEXT: retq
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; SSE2-LABEL: combine_nested_undef_test16:
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; SSE2: # BB#0:
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_nested_undef_test16:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_nested_undef_test16:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
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; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,1,0,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: combine_nested_undef_test16:
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; AVX: # BB#0:
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,3]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,1,0,3]
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; AVX-NEXT: retq
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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@ -892,16 +904,28 @@ define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
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}
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define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
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; SSE-LABEL: combine_nested_undef_test17:
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
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; SSE-NEXT: retq
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; SSE2-LABEL: combine_nested_undef_test17:
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; SSE2: # BB#0:
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_nested_undef_test17:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_nested_undef_test17:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,0,1]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: combine_nested_undef_test17:
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; AVX: # BB#0:
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; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,1]
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; AVX-NEXT: retq
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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@ -924,17 +948,30 @@ define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
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}
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define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
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; SSE-LABEL: combine_nested_undef_test19:
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,0]
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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; SSE2-LABEL: combine_nested_undef_test19:
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; SSE2: # BB#0:
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,0]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_nested_undef_test19:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,0]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_nested_undef_test19:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
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; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: combine_nested_undef_test19:
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; AVX: # BB#0:
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; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[0,0]
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,0,0,0]
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; AVX-NEXT: retq
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
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@ -942,17 +979,30 @@ define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
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}
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define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
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; SSE-LABEL: combine_nested_undef_test20:
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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; SSE2-LABEL: combine_nested_undef_test20:
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; SSE2: # BB#0:
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_nested_undef_test20:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_nested_undef_test20:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,0]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: combine_nested_undef_test20:
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; AVX: # BB#0:
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,0],xmm0[2,3]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,3,0]
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; AVX-NEXT: retq
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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@ -960,17 +1010,30 @@ define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
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}
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define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
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; SSE-LABEL: combine_nested_undef_test21:
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,1]
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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; SSE2-LABEL: combine_nested_undef_test21:
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; SSE2: # BB#0:
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,1]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_nested_undef_test21:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,1]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_nested_undef_test21:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
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; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: combine_nested_undef_test21:
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; AVX: # BB#0:
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,0],xmm0[1,1]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
||||
; AVX-NEXT: retq
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||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
|
||||
|
|
@ -1599,16 +1662,28 @@ define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
|
|||
}
|
||||
|
||||
define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: combine_test3b:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
|
||||
; SSE-NEXT: retq
|
||||
; SSE2-LABEL: combine_test3b:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_test3b:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_test3b:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
|
||||
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,2,3]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_test3b:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
|
||||
; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
|
||||
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,3,2,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
|
||||
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
|
||||
|
|
|
|||
Loading…
Reference in New Issue