Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics."
The instructions were being generated on architectures that don't support avx512. This reverts commit r229837. llvm-svn: 229942
This commit is contained in:
Eric Christopher
parent
06b32cdfed
commit
0d94fa98e5
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@ -3193,14 +3193,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty,
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llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_rndscale_ss : GCCBuiltin<"__builtin_ia32_rndscaless_mask">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_i8_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_rndscale_sd : GCCBuiltin<"__builtin_ia32_rndscalesd_mask">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_i8_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rndscale_ss : GCCBuiltin<"__builtin_ia32_rndscaless">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_rndscale_sd : GCCBuiltin<"__builtin_ia32_rndscalesd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtrndss">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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@ -17374,20 +17374,9 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget
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SDValue Src2 = Op.getOperand(2);
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SDValue Src0 = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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// There are 2 kinds of intrinsics in this group:
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// (1) With supress-all-exceptions (sae) - 6 operands
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// (2) With rounding mode and sae - 7 operands.
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if (Op.getNumOperands() == 6) {
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SDValue Sae = Op.getOperand(5);
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
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Sae),
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Mask, Src0, Subtarget, DAG);
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}
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assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
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SDValue RoundingMode = Op.getOperand(5);
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SDValue Sae = Op.getOperand(6);
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SDValue RoundingMode = Op.getOperand(5);
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
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RoundingMode, Sae),
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RoundingMode),
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Mask, Src0, Subtarget, DAG);
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}
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case INTR_TYPE_2OP_MASK: {
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@ -393,8 +393,7 @@ namespace llvm {
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FMSUB_RND,
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FNMSUB_RND,
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FMADDSUB_RND,
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FMSUBADD_RND,
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RNDSCALE,
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FMSUBADD_RND,
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// Compress and expand
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COMPRESS,
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@ -101,8 +101,6 @@ class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
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!if (!eq (EltTypeName, "f64"), SSEPackedDouble,
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SSEPackedInt));
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RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
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// A vector type of the same width with element type i32. This is used to
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// create the canonical constant zero node ImmAllZerosV.
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ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
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@ -4654,6 +4652,7 @@ let ExeDomain = d in {
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} // ExeDomain
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}
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defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
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loadv16f32, SSEPackedSingle>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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@ -4673,68 +4672,51 @@ def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
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FROUND_CURRENT)),
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(VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
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multiclass
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avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
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multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
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Operand x86memop, RegisterClass RC, Domain d> {
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let ExeDomain = d in {
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def r : AVX512AIi8<opc, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src2, i32u8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, EVEX_4V;
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let ExeDomain = _.ExeDomain in {
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defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
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"$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 imm:$src3), (i32 FROUND_CURRENT)))>;
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defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
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"$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 imm:$src3), (i32 FROUND_NO_EXC))), "{sae}">, EVEX_B;
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let mayLoad = 1 in
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defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
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"$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT (X86RndScale (_.VT _.RC:$src1),
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(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
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(i32 imm:$src3), (i32 FROUND_CURRENT)))>;
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}
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def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
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def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
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def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
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def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
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def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
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def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0x1))), _.FRC)>;
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def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0x2))), _.FRC)>;
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def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0x3))), _.FRC)>;
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def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0x4))), _.FRC)>;
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def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0xc))), _.FRC)>;
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def m : AVX512AIi8<opc, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32u8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, EVEX_4V;
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} // ExeDomain
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}
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defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
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AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
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defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
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SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
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defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
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AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
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defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
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SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
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let Predicates = [HasAVX512] in {
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def : Pat<(ffloor FR32X:$src),
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(VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
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def : Pat<(f64 (ffloor FR64X:$src)),
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(VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
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def : Pat<(f32 (fnearbyint FR32X:$src)),
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(VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
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def : Pat<(f64 (fnearbyint FR64X:$src)),
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(VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
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def : Pat<(f32 (fceil FR32X:$src)),
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(VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
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def : Pat<(f64 (fceil FR64X:$src)),
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(VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
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def : Pat<(f32 (frint FR32X:$src)),
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(VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
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def : Pat<(f64 (frint FR64X:$src)),
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(VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
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def : Pat<(f32 (ftrunc FR32X:$src)),
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(VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
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def : Pat<(f64 (ftrunc FR64X:$src)),
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(VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
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}
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def : Pat<(v16f32 (ffloor VR512:$src)),
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(VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
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@ -223,8 +223,6 @@ def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
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SDTCisVec<0>, SDTCisInt<2>]>;
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def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
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SDTCisVec<0>, SDTCisInt<3>]>;
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def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
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SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
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def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
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def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
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@ -301,7 +299,6 @@ def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
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def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
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def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
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def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
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def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
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SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
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@ -378,10 +378,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_mask_psrli_q, VSHIFT_MASK, X86ISD::VSRLI, 0),
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X86_INTRINSIC_DATA(avx512_mask_psrlv_d, INTR_TYPE_2OP_MASK, ISD::SRL, 0),
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X86_INTRINSIC_DATA(avx512_mask_psrlv_q, INTR_TYPE_2OP_MASK, ISD::SRL, 0),
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X86_INTRINSIC_DATA(avx512_mask_rndscale_sd, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::RNDSCALE, 0),
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X86_INTRINSIC_DATA(avx512_mask_rndscale_ss, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::RNDSCALE, 0),
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X86_INTRINSIC_DATA(avx512_mask_sub_pd_512, INTR_TYPE_2OP_MASK, ISD::FSUB,
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X86ISD::FSUB_RND),
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X86_INTRINSIC_DATA(avx512_mask_sub_ps_512, INTR_TYPE_2OP_MASK, ISD::FSUB,
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@ -400,8 +396,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_mask_ucmp_w_512, CMP_MASK_CC, X86ISD::CMPMU, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_sd, INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ss, INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_sd, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ss, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_sd, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RSQRT28, 0),
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@ -68,14 +68,6 @@ define <8 x double> @test7(<8 x double> %a) {
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ret <8 x double>%res
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}
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declare <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32, i32)
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define <2 x double> @test_rndsc_sd(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
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; CHECK: vrndscalesd $11, %xmm{{.*}} {%k1} ## encoding: [0x62,0xf3,0xfd,0x09,0x0b,0xd1,0x0b]
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%res = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 5, i32 11, i32 4)
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ret <2 x double>%res
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}
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declare <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float>, i32, <16 x float>, i16, i32)
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define <16 x float> @test8(<16 x float> %a) {
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@ -79,28 +79,3 @@ define <8 x double> @nearbyint_v8f64(<8 x double> %a) {
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ret <8 x double> %res
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}
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declare <8 x double> @llvm.nearbyint.v8f64(<8 x double> %p)
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define double @nearbyint_f64(double %a) {
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; CHECK-LABEL: nearbyint_f64
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; CHECK: vrndscalesd $12, {{.*}}encoding: [0x62,0xf3,0xfd,0x08,0x0b,0xc0,0x0c]
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%res = call double @llvm.nearbyint.f64(double %a)
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ret double %res
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}
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declare double @llvm.nearbyint.f64(double %p)
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define float @floor_f32(float %a) {
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; CHECK-LABEL: floor_f32
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; CHECK: vrndscaless $1, {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,0xc0,0x01]
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%res = call float @llvm.floor.f32(float %a)
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ret float %res
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}
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declare float @llvm.floor.f32(float %p)
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define float @floor_f32m(float* %aptr) {
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; CHECK-LABEL: floor_f32m
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; CHECK: vrndscaless $1, (%rdi), {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,0x07,0x01]
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%a = load float* %aptr, align 4
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%res = call float @llvm.floor.f32(float %a)
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ret float %res
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}
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