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0aa6a74a79
commit
0d4234416f
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@ -7743,31 +7743,6 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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if (VT.getSizeInBits() != 128)
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return SDValue();
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// For x86-32 machines, if we see an insert and then a shuffle in a v2i64
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// where the upper half is 0, it is advantageous to rewrite it as a build
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// vector of (0, val) so it can use movq.
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if (VT == MVT::v2i64) {
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SDValue In[2];
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In[0] = N->getOperand(0);
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In[1] = N->getOperand(1);
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int Idx0 = SVN->getMaskElt(0);
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int Idx1 = SVN->getMaskElt(1);
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// FIXME: can we take advantage of undef index?
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if (Idx0 >= 0 && Idx1 >= 0 &&
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In[Idx0/2].getOpcode() == ISD::INSERT_VECTOR_ELT &&
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In[Idx1/2].getOpcode() == ISD::BUILD_VECTOR) {
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ConstantSDNode* InsertVecIdx =
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dyn_cast<ConstantSDNode>(In[Idx0/2].getOperand(2));
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if (InsertVecIdx &&
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InsertVecIdx->getZExtValue() == (unsigned)(Idx0 % 2) &&
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isZeroNode(In[Idx1/2].getOperand(Idx1 % 2))) {
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return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
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In[Idx0/2].getOperand(1),
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In[Idx1/2].getOperand(Idx1 % 2));
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}
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}
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}
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// Try to combine a vector_shuffle into a 128-bit load.
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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LoadSDNode *LD = NULL;
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