diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index ab28120ba27a..8ded94d062a3 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1966,11 +1966,10 @@ bool BitSimplification::genExtractHalf(MachineInstr *MI,
     NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
     BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR)
         .addReg(L.Reg, 0, L.Sub);
-  } else if (!L.Low && Opc != Hexagon::S2_extractu) {
+  } else if (!L.Low && Opc != Hexagon::S2_lsr_i_r) {
     NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
-    BuildMI(B, MI, DL, HII.get(Hexagon::S2_extractu), NewR)
+    BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR)
         .addReg(L.Reg, 0, L.Sub)
-        .addImm(16)
         .addImm(16);
   }
   if (NewR == 0)
diff --git a/llvm/test/CodeGen/Hexagon/bit-extractu-half.ll b/llvm/test/CodeGen/Hexagon/bit-extractu-half.ll
new file mode 100644
index 000000000000..fec4a02d9269
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/bit-extractu-half.ll
@@ -0,0 +1,13 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Pick lsr (in bit-simplification) for extracting high halfword.
+; CHECK: lsr{{.*}}#16
+
+define i32 @foo(i32 %x) #0 {
+  %a = call i32 @llvm.hexagon.S2.extractu(i32 %x, i32 16, i32 16)
+  ret i32 %a
+}
+
+declare i32 @llvm.hexagon.S2.extractu(i32, i32, i32) #0
+
+attributes #0 = { nounwind readnone }
+