InstrItineraryData is already on the subtarget, no reason to

cache it on the target as well.

llvm-svn: 211818
This commit is contained in:
Eric Christopher 2014-06-27 00:13:43 +00:00
parent 009bff223b
commit 0d0b3600d8
2 changed files with 6 additions and 10 deletions

View File

@ -67,15 +67,12 @@ SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, Reloc::Model RM, CodeModel::Model CM,
CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32") , DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32"), Subtarget(TT, CPU, FS),
Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this), InstrInfo(Subtarget), TLInfo(*this), TSInfo(*this),
TSInfo(*this), FrameLowering(Subtarget) {
FrameLowering(Subtarget),
InstrItins(&Subtarget.getInstrItineraryData()) {
initAsmInfo(); initAsmInfo();
} }

View File

@ -33,7 +33,6 @@ class HexagonTargetMachine : public LLVMTargetMachine {
HexagonTargetLowering TLInfo; HexagonTargetLowering TLInfo;
HexagonSelectionDAGInfo TSInfo; HexagonSelectionDAGInfo TSInfo;
HexagonFrameLowering FrameLowering; HexagonFrameLowering FrameLowering;
const InstrItineraryData* InstrItins;
public: public:
HexagonTargetMachine(const Target &T, StringRef TT,StringRef CPU, HexagonTargetMachine(const Target &T, StringRef TT,StringRef CPU,
@ -52,7 +51,7 @@ public:
} }
const InstrItineraryData* getInstrItineraryData() const override { const InstrItineraryData* getInstrItineraryData() const override {
return InstrItins; return &getSubtargetImpl()->getInstrItineraryData();
} }