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R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove() 

We must constrain the destination register class of legalized operands
to a VGPR class or else the illegal operand may be folded back into
the instruction by the register coalescer.

This fixes a bug in add.ll that will be uncovered by future commits.

llvm-svn: 217249
This commit is contained in:
Tom Stellard 2014-09-05 14:08:01 +00:00
parent 80942a1b50
commit 0c93c9ecee
1 changed files with 5 additions and 4 deletions
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9
llvm/lib/Target/R600/SIInstrInfo.cpp
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@ -984,17 +984,18 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
const TargetRegisterClass *RC = RI.getRegClass(RCID);
unsigned Opcode = AMDGPU::V_MOV_B32_e32;
if (MO.isReg()) {
Opcode = AMDGPU::COPY;
} else if (RI.isSGPRClass(RC)) {
Opcode = AMDGPU::S_MOV_B32;
} else if (MO.isImm()) {
if (RC == &AMDGPU::VSrc_32RegClass)
Opcode = AMDGPU::S_MOV_B32;
}
const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) {
VRC = &AMDGPU::VReg_64RegClass;
} else {
VRC = &AMDGPU::VReg_32RegClass;
}
unsigned Reg = MRI.createVirtualRegister(VRC);
BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
Reg).addOperand(MO);