From 0bf68ae4348c35c209ffa978684a7297044130da Mon Sep 17 00:00:00 2001
From: Andrew Lenharth <andrewl@lenharth.org>
Date: Sun, 20 Nov 2005 21:41:10 +0000
Subject: [PATCH] The second patch of X86 support for read cycle counter.

llvm-svn: 24430
---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +++++++
 llvm/lib/Target/X86/X86ISelLowering.h   | 4 ++++
 llvm/lib/Target/X86/X86ISelPattern.cpp  | 5 +++++
 llvm/lib/Target/X86/X86InstrInfo.td     | 4 ++++
 4 files changed, 20 insertions(+)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e33bf956860c..aa221fbda3de 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -101,6 +101,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
   setOperationAction(ISD::CTPOP            , MVT::i32  , Expand);
   setOperationAction(ISD::CTTZ             , MVT::i32  , Expand);
   setOperationAction(ISD::CTLZ             , MVT::i32  , Expand);
+  setOperationAction(ISD::READCYCLECOUNTER , MVT::i64  , Custom);
 
   setOperationAction(ISD::READIO           , MVT::i1   , Expand);
   setOperationAction(ISD::READIO           , MVT::i8   , Expand);
@@ -912,5 +913,11 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
                        DAG.getSrcValue(NULL));
   }
+  case ISD::READCYCLECOUNTER: {
+    SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, MVT::Other, Op.getOperand(0));
+    SDOperand Lo = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32);
+    SDOperand Hi = DAG.getCopyFromReg(rd, X86::EDX, MVT::i32);
+    return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
+  }
   }
 }
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index b4468ac8a339..ccec6ea23f7c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -62,6 +62,10 @@ namespace llvm {
       /// LLVM.
       CALL,
       TAILCALL,
+      
+      /// RDTSC_DAG - This operation implements the lowering for 
+      /// readcyclecounter
+      RDTSC_DAG,
     };
   }
 
diff --git a/llvm/lib/Target/X86/X86ISelPattern.cpp b/llvm/lib/Target/X86/X86ISelPattern.cpp
index 58c60692b9d5..5c4594aa9ec9 100644
--- a/llvm/lib/Target/X86/X86ISelPattern.cpp
+++ b/llvm/lib/Target/X86/X86ISelPattern.cpp
@@ -3090,6 +3090,11 @@ void ISel::Select(SDOperand N) {
   default:
     Node->dump(); std::cerr << "\n";
     assert(0 && "Node not handled yet!");
+  case X86ISD::RDTSC_DAG:
+    Select(Node->getOperand(0)); //Chain
+    BuildMI(BB, X86::RDTSC, 0);
+    return;
+
   case ISD::EntryToken: return;  // Noop
   case ISD::TokenFactor:
     if (Node->getNumOperands() == 2) {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 40b2481ab4ac..0eaf337fd4ff 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -167,6 +167,10 @@ class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
 def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE">;        // PHI node.
 def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
 
+//FIXME: encode this correctly
+let Defs = [EAX, EDX] in
+  def RDTSC : I<0, Pseudo, (ops ), "rdtsc">; //in binary, this inst is 0x0f 0x31
+
 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN">;
 def ADJCALLSTACKUP   : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
                          "#ADJCALLSTACKUP">;