Hide more details in tablegen generated MCRegisterInfo ctor function.

llvm-svn: 134027
This commit is contained in:
Evan Cheng 2011-06-28 20:44:22 +00:00
parent df8974ef2f
commit 0beca53a29
14 changed files with 20 additions and 32 deletions

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@ -58,8 +58,7 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
const ARMSubtarget &sti) const ARMSubtarget &sti)
: ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc, : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti), TII(tii), STI(sti),
FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
BasePtr(ARM::R6) { BasePtr(ARM::R6) {

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@ -41,8 +41,7 @@
using namespace llvm; using namespace llvm;
AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
: AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc, : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
TII(tii) { TII(tii) {
} }

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@ -38,8 +38,7 @@ using namespace llvm;
BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st, BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
const TargetInstrInfo &tii) const TargetInstrInfo &tii)
: BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc, : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
Subtarget(st), Subtarget(st),
TII(tii) {} TII(tii) {}

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@ -189,8 +189,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget, SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
const TargetInstrInfo &tii) : const TargetInstrInfo &tii) :
SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc, SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
Subtarget(subtarget), Subtarget(subtarget),
TII(tii) TII(tii)
{ {

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@ -45,8 +45,7 @@ using namespace llvm;
MBlazeRegisterInfo:: MBlazeRegisterInfo::
MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii) MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
: MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc, : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) {} Subtarget(ST), TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g. /// getRegisterNumbering - Given the enum value for some register, e.g.

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@ -35,8 +35,7 @@ using namespace llvm;
// FIXME: Provide proper call frame setup / destroy opcodes. // FIXME: Provide proper call frame setup / destroy opcodes.
MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm, MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
const TargetInstrInfo &tii) const TargetInstrInfo &tii)
: MSP430GenRegisterInfo(MSP430RegDesc, MSP430RegInfoDesc, : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
TM(tm), TII(tii) { TM(tm), TII(tii) {
StackAlign = TM.getFrameLowering()->getStackAlignment(); StackAlign = TM.getFrameLowering()->getStackAlignment();
} }

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@ -44,8 +44,7 @@ using namespace llvm;
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST, MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
const TargetInstrInfo &tii) const TargetInstrInfo &tii)
: MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc, : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) {} Subtarget(ST), TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g. /// getRegisterNumbering - Given the enum value for some register, e.g.

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@ -25,7 +25,7 @@ using namespace llvm;
PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM, PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
const TargetInstrInfo &TII) const TargetInstrInfo &TII)
: PTXGenRegisterInfo(PTXRegDesc, PTXRegInfoDesc) { : PTXGenRegisterInfo() {
} }
void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,

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@ -114,8 +114,7 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
const TargetInstrInfo &tii) const TargetInstrInfo &tii)
: PPCGenRegisterInfo(PPCRegDesc, PPCRegInfoDesc, : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) { Subtarget(ST), TII(tii) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;

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@ -32,8 +32,7 @@ using namespace llvm;
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
const TargetInstrInfo &tii) const TargetInstrInfo &tii)
: SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc, : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
Subtarget(st), TII(tii) { Subtarget(st), TII(tii) {
} }

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@ -34,8 +34,7 @@ using namespace llvm;
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm, SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
const SystemZInstrInfo &tii) const SystemZInstrInfo &tii)
: SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc, : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
TM(tm), TII(tii) { TM(tm), TII(tii) {
} }

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@ -54,8 +54,7 @@ ForceStackAlign("force-align-stack",
X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
const TargetInstrInfo &tii) const TargetInstrInfo &tii)
: X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc, : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
tm.getSubtarget<X86Subtarget>().is64Bit() ?
X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN64 :
X86::ADJCALLSTACKDOWN32, X86::ADJCALLSTACKDOWN32,
tm.getSubtarget<X86Subtarget>().is64Bit() ? tm.getSubtarget<X86Subtarget>().is64Bit() ?

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@ -40,8 +40,7 @@
using namespace llvm; using namespace llvm;
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
: XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc, : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
TII(tii) { TII(tii) {
} }

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@ -215,8 +215,7 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
<< " explicit " << ClassName << " explicit " << ClassName
<< "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, " << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, " << " virtual int getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const;\n" << "unsigned Flavour) const;\n"
<< " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
@ -549,8 +548,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << " };\n"; OS << " };\n";
// Emit extra information about registers. // Emit extra information about registers.
const std::string &TargetName = Target.getName();
OS << "\n static const TargetRegisterInfoDesc " OS << "\n static const TargetRegisterInfoDesc "
<< Target.getName() << "RegInfoDesc[] = " << TargetName << "RegInfoDesc[] = "
<< "{ // Extra Descriptors\n"; << "{ // Extra Descriptors\n";
OS << " { 0, 0 },\n"; OS << " { 0, 0 },\n";
@ -660,13 +660,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the constructor of the class... // Emit the constructor of the class...
OS << ClassName << "::" << ClassName OS << ClassName << "::" << ClassName
<< "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, " << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
<< " : TargetRegisterInfo(ID"
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
<< " SubRegIndexTable,\n" << " SubRegIndexTable,\n"
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n" << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
<< " InitMCRegisterInfo(D, " << Regs.size()+1 << ");\n" << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ");\n"
<< "}\n\n"; << "}\n\n";
// Collect all information about dwarf register numbers // Collect all information about dwarf register numbers