Made the lldb_private::Opcode struct into a real boy... I mean class.
Modified the Disassembler::Instruction base class to contain an Opcode instance so that we can know the bytes for an instruction without needing to keep the data around. Modified the DisassemblerLLVM's instruction class to correctly extract the opcode bytes if all goes well. llvm-svn: 128248
This commit is contained in:
Greg Clayton
parent
ceef55466a
commit
0ae962735f
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@ -19,6 +19,7 @@
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#include "lldb/lldb-private.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/ArchSpec.h"
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#include "lldb/Core/Opcode.h"
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#include "lldb/Core/PluginInterface.h"
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namespace lldb_private {
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@ -27,6 +28,7 @@ class Instruction
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{
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public:
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Instruction (const Address &addr);
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Instruction (const Address &addr, const Opcode &opcode);
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virtual
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~Instruction();
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@ -59,10 +61,19 @@ public:
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DoesBranch () const = 0;
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virtual size_t
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Extract (const DataExtractor& data, uint32_t data_offset) = 0;
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Extract (const Disassembler &disassembler,
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const DataExtractor& data,
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uint32_t data_offset) = 0;
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const Opcode &
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GetOpcode () const
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{
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return m_opcode;
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}
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protected:
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Address m_addr; // The section offset address of this instruction
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Opcode m_opcode; // The opcode for this instruction
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};
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@ -206,6 +217,12 @@ public:
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const InstructionList &
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GetInstructionList () const;
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const ArchSpec &
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GetArchitecture () const
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{
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return m_arch;
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}
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protected:
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//------------------------------------------------------------------
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// Classes that inherit from Disassembler can see and modify these
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@ -12,6 +12,7 @@
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#include "lldb/lldb-public.h"
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#include "lldb/Core/PluginInterface.h"
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#include "lldb/Core/Opcode.h"
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//----------------------------------------------------------------------
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/// @class EmulateInstruction EmulateInstruction.h "lldb/Core/EmulateInstruction.h"
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@ -432,22 +433,10 @@ public:
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return m_byte_order;
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}
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uint64_t
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OpcodeAsUnsigned (bool *success_ptr)
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const Opcode &
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GetOpcode () const
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{
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if (success_ptr)
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*success_ptr = true;
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switch (m_opcode.type)
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{
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case eOpcode8: return m_opcode.data.inst8;
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case eOpcode16: return m_opcode.data.inst16;
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case eOpcode32: return m_opcode.data.inst32;
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case eOpcode64: return m_opcode.data.inst64;
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case eOpcodeBytes: break;
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}
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if (success_ptr)
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*success_ptr = false;
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return 0;
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return m_opcode;
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}
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protected:
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@ -0,0 +1,217 @@
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//===-- Opcode.h ------------------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef lldb_Opcode_h
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#define lldb_Opcode_h
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// C Includes
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// C++ Includes
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// Other libraries and framework includes
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// Project includes
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#include "lldb/lldb-public.h"
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namespace lldb_private {
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class Opcode
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{
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public:
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enum Type
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{
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eTypeInvalid,
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eType8,
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eType16,
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eType32,
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eType64,
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eTypeBytes
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};
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Opcode () : m_type (eTypeInvalid)
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{
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}
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Opcode (uint8_t inst) : m_type (eType8)
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{
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m_data.inst8 = inst;
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}
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Opcode (uint16_t inst) : m_type (eType16)
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{
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m_data.inst16 = inst;
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}
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Opcode (uint32_t inst) : m_type (eType32)
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{
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m_data.inst32 = inst;
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}
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Opcode (uint64_t inst) : m_type (eType64)
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{
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m_data.inst64 = inst;
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}
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Opcode (uint8_t *bytes, size_t length)
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{
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SetOpcodeBytes (bytes, length);
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}
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Opcode::Type
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GetType () const
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{
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return m_type;
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}
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uint8_t
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GetOpcode8 (uint8_t invalid_opcode = UINT8_MAX) const
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{
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switch (m_type)
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{
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case Opcode::eTypeInvalid: break;
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case Opcode::eType8: return m_data.inst8;
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case Opcode::eType16: break;
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case Opcode::eType32: break;
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case Opcode::eType64: break;
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case Opcode::eTypeBytes: break;
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break;
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}
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return invalid_opcode;
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}
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uint16_t
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GetOpcode16 (uint16_t invalid_opcode = UINT16_MAX) const
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{
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switch (m_type)
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{
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case Opcode::eTypeInvalid: break;
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case Opcode::eType8: return m_data.inst8;
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case Opcode::eType16: return m_data.inst16;
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case Opcode::eType32: break;
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case Opcode::eType64: break;
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case Opcode::eTypeBytes: break;
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}
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return invalid_opcode;
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}
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uint32_t
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GetOpcode32 (uint32_t invalid_opcode = UINT32_MAX) const
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{
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switch (m_type)
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{
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case Opcode::eTypeInvalid: break;
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case Opcode::eType8: return m_data.inst8;
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case Opcode::eType16: return m_data.inst16;
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case Opcode::eType32: return m_data.inst32;
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case Opcode::eType64: break;
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case Opcode::eTypeBytes: break;
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}
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return invalid_opcode;
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}
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uint64_t
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GetOpcode64 (uint64_t invalid_opcode = UINT64_MAX) const
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{
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switch (m_type)
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{
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case Opcode::eTypeInvalid: break;
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case Opcode::eType8: return m_data.inst8;
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case Opcode::eType16: return m_data.inst16;
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case Opcode::eType32: return m_data.inst32;
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case Opcode::eType64: return m_data.inst64;
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case Opcode::eTypeBytes: break;
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}
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return invalid_opcode;
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}
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void
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SetOpcode8 (uint8_t inst)
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{
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m_type = eType8;
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m_data.inst8 = inst;
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}
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void
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SetOpcode16 (uint16_t inst)
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{
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m_type = eType16;
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m_data.inst16 = inst;
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}
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void
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SetOpcode32 (uint32_t inst)
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{
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m_type = eType32;
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m_data.inst32 = inst;
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}
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void
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SetOpcode64 (uint64_t inst)
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{
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m_type = eType64;
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m_data.inst64 = inst;
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}
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void
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SetOpcodeBytes (const void *bytes, size_t length)
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{
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if (bytes && length > 0)
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{
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m_type = eTypeBytes;
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assert (length < sizeof (m_data.inst.bytes));
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memcpy (m_data.inst.bytes, bytes, length);
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}
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else
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{
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m_type = eTypeInvalid;
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m_data.inst.length = 0;
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}
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}
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const void *
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GetOpcodeBytes () const
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{
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if (m_type == Opcode::eTypeBytes)
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return m_data.inst.bytes;
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return NULL;
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}
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uint32_t
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GetByteSize () const
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{
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switch (m_type)
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{
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case Opcode::eTypeInvalid: break;
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case Opcode::eType8: return sizeof(m_data.inst8);
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case Opcode::eType16: return sizeof(m_data.inst16);
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case Opcode::eType32: return sizeof(m_data.inst32);
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case Opcode::eType64: return sizeof(m_data.inst64);
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case Opcode::eTypeBytes: return m_data.inst.length;
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}
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return 0;
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}
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protected:
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Opcode::Type m_type;
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union
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{
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uint8_t inst8;
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uint16_t inst16;
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uint32_t inst32;
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uint64_t inst64;
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struct
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{
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uint8_t length;
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uint8_t bytes[16]; // This must be big enough to handle any opcode for any supported target.
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} inst;
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} m_data;
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};
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} // namespace lldb_private
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#endif // lldb_Opcode_h
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@ -65,33 +65,6 @@ namespace lldb_private
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// pass it.
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} OptionDefinition;
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enum OpcodeType
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{
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eOpcode8,
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eOpcode16,
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eOpcode32,
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eOpcode64,
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eOpcodeBytes
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};
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struct Opcode
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{
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OpcodeType type;
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union
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{
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uint8_t inst8;
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uint16_t inst16;
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uint32_t inst32;
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uint64_t inst64;
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struct
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{
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uint8_t length;
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uint8_t bytes[16]; // This must be big enough to handle any opcode for any supported target.
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} inst;
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} data;
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};
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} // namespace lldb_private
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#endif // #if defined(__cplusplus)
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@ -16,6 +16,8 @@
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264A97BF133918BC0017F0BE /* PlatformRemoteGDBServer.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 264A97BD133918BC0017F0BE /* PlatformRemoteGDBServer.cpp */; };
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264A97C0133918BC0017F0BE /* PlatformRemoteGDBServer.h in Headers */ = {isa = PBXBuildFile; fileRef = 264A97BE133918BC0017F0BE /* PlatformRemoteGDBServer.h */; };
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265ABF6310F42EE900531910 /* DebugSymbols.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 265ABF6210F42EE900531910 /* DebugSymbols.framework */; };
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26651A16133BF9CD005B64B7 /* Opcode.h in Headers */ = {isa = PBXBuildFile; fileRef = 26651A15133BF9CC005B64B7 /* Opcode.h */; };
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26651A18133BF9E0005B64B7 /* Opcode.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 26651A17133BF9DF005B64B7 /* Opcode.cpp */; };
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2668020E115FD12C008E1FE4 /* lldb-defines.h in Headers */ = {isa = PBXBuildFile; fileRef = 26BC7C2510F1B3BC00F91463 /* lldb-defines.h */; settings = {ATTRIBUTES = (Public, ); }; };
|
||||
2668020F115FD12C008E1FE4 /* lldb-enumerations.h in Headers */ = {isa = PBXBuildFile; fileRef = 26BC7C2610F1B3BC00F91463 /* lldb-enumerations.h */; settings = {ATTRIBUTES = (Public, ); }; };
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26680214115FD12C008E1FE4 /* lldb-types.h in Headers */ = {isa = PBXBuildFile; fileRef = 26BC7C2910F1B3BC00F91463 /* lldb-types.h */; settings = {ATTRIBUTES = (Public, ); }; };
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|
|
@ -631,6 +633,8 @@
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2660D9F711922A1300958FBD /* StringExtractor.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = StringExtractor.h; path = source/Utility/StringExtractor.h; sourceTree = "<group>"; };
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2660D9FE11922A7F00958FBD /* ThreadPlanStepUntil.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = ThreadPlanStepUntil.cpp; path = source/Target/ThreadPlanStepUntil.cpp; sourceTree = "<group>"; };
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26651A14133BEC76005B64B7 /* lldb-public.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = "lldb-public.h"; path = "include/lldb/lldb-public.h"; sourceTree = "<group>"; };
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26651A15133BF9CC005B64B7 /* Opcode.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = Opcode.h; path = include/lldb/Core/Opcode.h; sourceTree = "<group>"; };
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26651A17133BF9DF005B64B7 /* Opcode.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Opcode.cpp; path = source/Core/Opcode.cpp; sourceTree = "<group>"; };
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26680207115FD0ED008E1FE4 /* LLDB.framework */ = {isa = PBXFileReference; explicitFileType = wrapper.framework; includeInIndex = 0; path = LLDB.framework; sourceTree = BUILT_PRODUCTS_DIR; };
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266960591199F4230075C61A /* build-llvm.pl */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.script.perl; path = "build-llvm.pl"; sourceTree = "<group>"; };
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2669605A1199F4230075C61A /* build-swig-wrapper-classes.sh */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.script.sh; path = "build-swig-wrapper-classes.sh"; sourceTree = "<group>"; };
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@ -1832,6 +1836,8 @@
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26BC7E8210F1B85900F91463 /* ModuleChild.cpp */,
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26BC7D6C10F1B77400F91463 /* ModuleList.h */,
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26BC7E8310F1B85900F91463 /* ModuleList.cpp */,
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26651A15133BF9CC005B64B7 /* Opcode.h */,
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26651A17133BF9DF005B64B7 /* Opcode.cpp */,
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26BC7D7010F1B77400F91463 /* PluginInterface.h */,
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26BC7D7110F1B77400F91463 /* PluginManager.h */,
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26BC7E8A10F1B85900F91463 /* PluginManager.cpp */,
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@ -2521,6 +2527,7 @@
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26744EF41338317700EF765A /* GDBRemoteCommunicationServer.h in Headers */,
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264A97C0133918BC0017F0BE /* PlatformRemoteGDBServer.h in Headers */,
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2697A54E133A6305004E4240 /* PlatformDarwin.h in Headers */,
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26651A16133BF9CD005B64B7 /* Opcode.h in Headers */,
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||||
);
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runOnlyForDeploymentPostprocessing = 0;
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||||
};
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@ -3080,6 +3087,7 @@
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26744EF31338317700EF765A /* GDBRemoteCommunicationServer.cpp in Sources */,
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264A97BF133918BC0017F0BE /* PlatformRemoteGDBServer.cpp in Sources */,
|
||||
2697A54D133A6305004E4240 /* PlatformDarwin.cpp in Sources */,
|
||||
26651A18133BF9E0005B64B7 /* Opcode.cpp in Sources */,
|
||||
);
|
||||
runOnlyForDeploymentPostprocessing = 0;
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||||
};
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||||
|
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@ -468,6 +468,14 @@ Disassembler::Disassemble
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Instruction::Instruction(const Address &addr) :
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m_addr (addr)
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{
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::memset (&m_opcode, 0, sizeof (m_opcode));
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}
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Instruction::Instruction(const Address &addr, const Opcode &opcode) :
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m_addr (addr),
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m_opcode (opcode)
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{
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}
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|
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@ -59,9 +59,9 @@ EmulateInstruction::EmulateInstruction
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m_write_mem_callback (write_mem_callback),
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m_read_reg_callback (read_reg_callback),
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m_write_reg_callback (write_reg_callback),
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m_opcode (),
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m_opcode_pc (LLDB_INVALID_ADDRESS)
|
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{
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::memset (&m_opcode, 0, sizeof (m_opcode));
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}
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uint64_t
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|
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@ -0,0 +1,18 @@
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//===-- Baton.cpp -----------------------------------------------*- C++ -*-===//
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//
|
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// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
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|
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#include "lldb/Core/Opcode.h"
|
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|
||||
// C Includes
|
||||
// C++ Includes
|
||||
// Other libraries and framework includes
|
||||
// Project includes
|
||||
|
||||
using namespace lldb;
|
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using namespace lldb_private;
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@ -74,7 +74,7 @@ static int IPRegisterReader(uint64_t *value, unsigned regID, void* arg)
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return -1;
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}
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DisassemblerLLVM::InstructionLLVM::InstructionLLVM (EDDisassemblerRef disassembler, const Address &addr) :
|
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DisassemblerLLVM::InstructionLLVM::InstructionLLVM (const Address &addr, EDDisassemblerRef disassembler) :
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||||
Instruction (addr),
|
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m_disassembler (disassembler)
|
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{
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||||
|
|
@ -334,10 +334,41 @@ DisassemblerLLVM::InstructionLLVM::GetByteSize() const
|
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}
|
||||
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||||
size_t
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DisassemblerLLVM::InstructionLLVM::Extract(const DataExtractor &data, uint32_t data_offset)
|
||||
DisassemblerLLVM::InstructionLLVM::Extract (const Disassembler &disassembler,
|
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const lldb_private::DataExtractor &data,
|
||||
uint32_t data_offset)
|
||||
{
|
||||
if (EDCreateInsts(&m_inst, 1, m_disassembler, DataExtractorByteReader, data_offset, (void*)(&data)))
|
||||
return EDInstByteSize(m_inst);
|
||||
{
|
||||
const int byte_size = EDInstByteSize(m_inst);
|
||||
uint32_t offset = data_offset;
|
||||
// Make a copy of the opcode in m_opcode
|
||||
switch (disassembler.GetArchitecture().GetMachine())
|
||||
{
|
||||
case llvm::Triple::x86:
|
||||
case llvm::Triple::x86_64:
|
||||
m_opcode.SetOpcodeBytes (data.PeekData (data_offset, byte_size), byte_size);
|
||||
break;
|
||||
|
||||
case llvm::Triple::arm:
|
||||
assert (byte_size == 4);
|
||||
m_opcode.SetOpcode32 (data.GetU32 (&offset));
|
||||
break;
|
||||
|
||||
case llvm::Triple::thumb:
|
||||
assert ((byte_size == 2) || (byte_size == 4));
|
||||
if (byte_size == 2)
|
||||
m_opcode.SetOpcode16 (data.GetU16 (&offset));
|
||||
else
|
||||
m_opcode.SetOpcode32 (data.GetU32 (&offset));
|
||||
break;
|
||||
|
||||
default:
|
||||
assert (!"This shouldn't happen since we control the architecture we allow DisassemblerLLVM to be created for");
|
||||
break;
|
||||
}
|
||||
return byte_size;
|
||||
}
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -430,10 +461,10 @@ DisassemblerLLVM::DecodeInstructions
|
|||
if (inst_addr.GetAddressClass () == eAddressClassCodeAlternateISA)
|
||||
use_thumb = true;
|
||||
}
|
||||
InstructionSP inst_sp (new InstructionLLVM (use_thumb ? m_disassembler_thumb : m_disassembler,
|
||||
inst_addr));
|
||||
InstructionSP inst_sp (new InstructionLLVM (inst_addr,
|
||||
use_thumb ? m_disassembler_thumb : m_disassembler));
|
||||
|
||||
size_t inst_byte_size = inst_sp->Extract (data, data_offset);
|
||||
size_t inst_byte_size = inst_sp->Extract (*this, data, data_offset);
|
||||
|
||||
if (inst_byte_size == 0)
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,8 @@ public:
|
|||
class InstructionLLVM : public lldb_private::Instruction
|
||||
{
|
||||
public:
|
||||
InstructionLLVM(EDDisassemblerRef disassembler, const lldb_private::Address &addr);
|
||||
InstructionLLVM (const lldb_private::Address &addr,
|
||||
EDDisassemblerRef disassembler);
|
||||
|
||||
virtual
|
||||
~InstructionLLVM();
|
||||
|
|
@ -42,7 +43,8 @@ public:
|
|||
GetByteSize() const;
|
||||
|
||||
size_t
|
||||
Extract (const lldb_private::DataExtractor &data,
|
||||
Extract (const Disassembler &disassembler,
|
||||
const lldb_private::DataExtractor &data,
|
||||
uint32_t data_offset);
|
||||
|
||||
protected:
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -125,10 +125,10 @@ public:
|
|||
ArchVersion();
|
||||
|
||||
bool
|
||||
ConditionPassed ();
|
||||
ConditionPassed (const uint32_t opcode);
|
||||
|
||||
uint32_t
|
||||
CurrentCond ();
|
||||
CurrentCond (const uint32_t opcode);
|
||||
|
||||
// InITBlock - Returns true if we're in Thumb mode and inside an IT Block.
|
||||
bool InITBlock();
|
||||
|
|
@ -301,7 +301,7 @@ protected:
|
|||
uint32_t variants;
|
||||
EmulateInstructionARM::ARMEncoding encoding;
|
||||
ARMInstrSize size;
|
||||
bool (EmulateInstructionARM::*callback) (EmulateInstructionARM::ARMEncoding encoding);
|
||||
bool (EmulateInstructionARM::*callback) (const uint32_t opcode, const EmulateInstructionARM::ARMEncoding encoding);
|
||||
const char *name;
|
||||
} ARMOpcode;
|
||||
|
||||
|
|
@ -314,423 +314,423 @@ protected:
|
|||
|
||||
// A8.6.123 PUSH
|
||||
bool
|
||||
EmulatePUSH (ARMEncoding encoding);
|
||||
EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.122 POP
|
||||
bool
|
||||
EmulatePOP (ARMEncoding encoding);
|
||||
EmulatePOP (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.8 ADD (SP plus immediate)
|
||||
bool
|
||||
EmulateADDRdSPImm (ARMEncoding encoding);
|
||||
EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp
|
||||
bool
|
||||
EmulateMOVRdSP (ARMEncoding encoding);
|
||||
EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.97 MOV (register) -- move from r8-r15 to r0-r7
|
||||
bool
|
||||
EmulateMOVLowHigh (ARMEncoding encoding);
|
||||
EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.59 LDR (literal)
|
||||
bool
|
||||
EmulateLDRRtPCRelative (ARMEncoding encoding);
|
||||
EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.8 ADD (SP plus immediate)
|
||||
bool
|
||||
EmulateADDSPImm (ARMEncoding encoding);
|
||||
EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.9 ADD (SP plus register)
|
||||
bool
|
||||
EmulateADDSPRm (ARMEncoding encoding);
|
||||
EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.23 BL, BLX (immediate)
|
||||
bool
|
||||
EmulateBLXImmediate (ARMEncoding encoding);
|
||||
EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.24 BLX (register)
|
||||
bool
|
||||
EmulateBLXRm (ARMEncoding encoding);
|
||||
EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.25 BX
|
||||
bool
|
||||
EmulateBXRm (ARMEncoding encoding);
|
||||
EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.26 BXJ
|
||||
bool
|
||||
EmulateBXJRm (ARMEncoding encoding);
|
||||
EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip
|
||||
bool
|
||||
EmulateSUBR7IPImm (ARMEncoding encoding);
|
||||
EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.215 SUB (SP minus immediate) -- Rd == ip
|
||||
bool
|
||||
EmulateSUBIPSPImm (ARMEncoding encoding);
|
||||
EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.215 SUB (SP minus immediate)
|
||||
bool
|
||||
EmulateSUBSPImm (ARMEncoding encoding);
|
||||
EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.194 STR (immediate, ARM) -- Rn == sp
|
||||
bool
|
||||
EmulateSTRRtSP (ARMEncoding encoding);
|
||||
EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.355 VPUSH
|
||||
bool
|
||||
EmulateVPUSH (ARMEncoding encoding);
|
||||
EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.354 VPOP
|
||||
bool
|
||||
EmulateVPOP (ARMEncoding encoding);
|
||||
EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.218 SVC (previously SWI)
|
||||
bool
|
||||
EmulateSVC (ARMEncoding encoding);
|
||||
EmulateSVC (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.50 IT
|
||||
bool
|
||||
EmulateIT (ARMEncoding encoding);
|
||||
EmulateIT (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.16 B
|
||||
bool
|
||||
EmulateB (ARMEncoding encoding);
|
||||
EmulateB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.27 CBNZ, CBZ
|
||||
bool
|
||||
EmulateCB (ARMEncoding encoding);
|
||||
EmulateCB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.226 TBB, TBH
|
||||
bool
|
||||
EmulateTB (ARMEncoding encoding);
|
||||
EmulateTB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.4 ADD (immediate, Thumb)
|
||||
bool
|
||||
EmulateADDImmThumb (ARMEncoding encoding);
|
||||
EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.5 ADD (immediate, ARM)
|
||||
bool
|
||||
EmulateADDImmARM (ARMEncoding encoding);
|
||||
EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.6 ADD (register)
|
||||
bool
|
||||
EmulateADDReg (ARMEncoding encoding);
|
||||
EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.97 MOV (register)
|
||||
bool
|
||||
EmulateMOVRdRm (ARMEncoding encoding);
|
||||
EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.96 MOV (immediate)
|
||||
bool
|
||||
EmulateMOVRdImm (ARMEncoding encoding);
|
||||
EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.35 CMP (immediate)
|
||||
bool
|
||||
EmulateCMPImm (ARMEncoding encoding);
|
||||
EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.36 CMP (register)
|
||||
bool
|
||||
EmulateCMPReg (ARMEncoding encoding);
|
||||
EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.14 ASR (immediate)
|
||||
bool
|
||||
EmulateASRImm (ARMEncoding encoding);
|
||||
EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.15 ASR (register)
|
||||
bool
|
||||
EmulateASRReg (ARMEncoding encoding);
|
||||
EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.88 LSL (immediate)
|
||||
bool
|
||||
EmulateLSLImm (ARMEncoding encoding);
|
||||
EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.89 LSL (register)
|
||||
bool
|
||||
EmulateLSLReg (ARMEncoding encoding);
|
||||
EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.90 LSR (immediate)
|
||||
bool
|
||||
EmulateLSRImm (ARMEncoding encoding);
|
||||
EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.91 LSR (register)
|
||||
bool
|
||||
EmulateLSRReg (ARMEncoding encoding);
|
||||
EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.139 ROR (immediate)
|
||||
bool
|
||||
EmulateRORImm (ARMEncoding encoding);
|
||||
EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.140 ROR (register)
|
||||
bool
|
||||
EmulateRORReg (ARMEncoding encoding);
|
||||
EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.141 RRX
|
||||
bool
|
||||
EmulateRRX (ARMEncoding encoding);
|
||||
EmulateRRX (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// Helper method for ASR, LSL, LSR, ROR (immediate), and RRX
|
||||
bool
|
||||
EmulateShiftImm (ARMEncoding encoding, ARM_ShifterType shift_type);
|
||||
EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
|
||||
|
||||
// Helper method for ASR, LSL, LSR, and ROR (register)
|
||||
bool
|
||||
EmulateShiftReg (ARMEncoding encoding, ARM_ShifterType shift_type);
|
||||
EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
|
||||
|
||||
// A8.6.53 LDM/LDMIA/LDMFD
|
||||
bool
|
||||
EmulateLDM (ARMEncoding encoding);
|
||||
EmulateLDM (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.54 LDMDA/LDMFA
|
||||
bool
|
||||
EmulateLDMDA (ARMEncoding encoding);
|
||||
EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.55 LDMDB/LDMEA
|
||||
bool
|
||||
EmulateLDMDB (ARMEncoding encoding);
|
||||
EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.56 LDMIB/LDMED
|
||||
bool
|
||||
EmulateLDMIB (ARMEncoding encoding);
|
||||
EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.57 LDR (immediate, Thumb) -- Encoding T1
|
||||
bool
|
||||
EmulateLDRRtRnImm (ARMEncoding encoding);
|
||||
EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.188 STM/STMIA/STMEA
|
||||
bool
|
||||
EmulateSTM (ARMEncoding encoding);
|
||||
EmulateSTM (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.189 STMDA/STMED
|
||||
bool
|
||||
EmulateSTMDA (ARMEncoding encoding);
|
||||
EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.190 STMDB/STMFD
|
||||
bool
|
||||
EmulateSTMDB (ARMEncoding encoding);
|
||||
EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.191 STMIB/STMFA
|
||||
bool
|
||||
EmulateSTMIB (ARMEncoding encoding);
|
||||
EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.192 STR (immediate, Thumb)
|
||||
bool
|
||||
EmulateSTRThumb(ARMEncoding encoding);
|
||||
EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.194 STR (register)
|
||||
bool
|
||||
EmulateSTRRegister (ARMEncoding encoding);
|
||||
EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.195 STRB (immediate, Thumb)
|
||||
bool
|
||||
EmulateSTRBThumb (ARMEncoding encoding);
|
||||
EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.207 STRH (register)
|
||||
bool
|
||||
EmulateSTRHRegister (ARMEncoding encoding);
|
||||
EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.1 ADC (immediate)
|
||||
bool
|
||||
EmulateADCImm (ARMEncoding encoding);
|
||||
EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.2 ADC (Register)
|
||||
bool
|
||||
EmulateADCReg (ARMEncoding encoding);
|
||||
EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.10 ADR
|
||||
bool
|
||||
EmulateADR (ARMEncoding encoding);
|
||||
EmulateADR (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.11 AND (immediate)
|
||||
bool
|
||||
EmulateANDImm (ARMEncoding encoding);
|
||||
EmulateANDImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.12 AND (register)
|
||||
bool
|
||||
EmulateANDReg (ARMEncoding encoding);
|
||||
EmulateANDReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.19 BIC (immediate)
|
||||
bool
|
||||
EmulateBICImm (ARMEncoding encoding);
|
||||
EmulateBICImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.20 BIC (register)
|
||||
bool
|
||||
EmulateBICReg (ARMEncoding encoding);
|
||||
EmulateBICReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.26 BXJ
|
||||
bool
|
||||
EmulateBXJ (ARMEncoding encoding);
|
||||
EmulateBXJ (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.32 CMN (immediate)
|
||||
bool
|
||||
EmulateCMNImm (ARMEncoding encoding);
|
||||
EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.33 CMN (register)
|
||||
bool
|
||||
EmulateCMNReg (ARMEncoding encoding);
|
||||
EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.44 EOR (immediate)
|
||||
bool
|
||||
EmulateEORImm (ARMEncoding encoding);
|
||||
EmulateEORImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.45 EOR (register)
|
||||
bool
|
||||
EmulateEORReg (ARMEncoding encoding);
|
||||
EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.58 LDR (immediate, ARM) - Encoding A1
|
||||
bool
|
||||
EmulateLDRImmediateARM (ARMEncoding encoding);
|
||||
EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.60 LDR (register) - Encoding T1, T2, A1
|
||||
bool
|
||||
EmulateLDRRegister (ARMEncoding encoding);
|
||||
EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2
|
||||
bool
|
||||
EmulateLDRBImmediate (ARMEncoding encoding);
|
||||
EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.63 LDRB (literal) - Encoding T1
|
||||
bool
|
||||
EmulateLDRBLiteral (ARMEncoding encoding);
|
||||
EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.64 LDRB (register) - Encoding T1
|
||||
bool
|
||||
EmulateLDRBRegister (ARMEncoding encoding);
|
||||
EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2
|
||||
bool
|
||||
EmulateLDRHImmediate (ARMEncoding encoding);
|
||||
EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.75 LDRH (literal) - Encoding T1
|
||||
bool
|
||||
EmulateLDRHLiteral (ARMEncoding encoding);
|
||||
EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.76 LDRH (register) - Encoding T1, T2
|
||||
bool
|
||||
EmulateLDRHRegister (ARMEncoding encoding);
|
||||
EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.78 LDRSB (immediate) - Encoding T1
|
||||
bool
|
||||
EmulateLDRSBImmediate (ARMEncoding encoding);
|
||||
EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.79 LDRSB (literal) - Encoding T1
|
||||
bool
|
||||
EmulateLDRSBLiteral (ARMEncoding encoding);
|
||||
EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.80 LDRSB (register) - Encoding T1, T2
|
||||
bool
|
||||
EmulateLDRSBRegister (ARMEncoding encoding);
|
||||
EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.82 LDRSH (immediate) - Encoding T1
|
||||
bool
|
||||
EmulateLDRSHImmediate (ARMEncoding encoding);
|
||||
EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.83 LDRSH (literal) - Encoding T1
|
||||
bool
|
||||
EmulateLDRSHLiteral (ARMEncoding encoding);
|
||||
EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.84 LDRSH (register) - Encoding T1, T2
|
||||
bool
|
||||
EmulateLDRSHRegister (ARMEncoding encoding);
|
||||
EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.105 MUL
|
||||
bool
|
||||
EmulateMUL (ARMEncoding encoding);
|
||||
EmulateMUL (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.106 MVN (immediate)
|
||||
bool
|
||||
EmulateMVNImm (ARMEncoding encoding);
|
||||
EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.107 MVN (register)
|
||||
bool
|
||||
EmulateMVNReg (ARMEncoding encoding);
|
||||
EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.113 ORR (immediate)
|
||||
bool
|
||||
EmulateORRImm (ARMEncoding encoding);
|
||||
EmulateORRImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.114 ORR (register)
|
||||
bool
|
||||
EmulateORRReg (ARMEncoding encoding);
|
||||
EmulateORRReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1
|
||||
bool
|
||||
EmulatePLDImmediate (ARMEncoding encoding);
|
||||
EmulatePLDImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.119 PLI (immediate,literal) - Encoding T3, A1
|
||||
bool
|
||||
EmulatePLIImmediate (ARMEncoding encoding);
|
||||
EmulatePLIImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.120 PLI (register) - Encoding T1, A1
|
||||
bool
|
||||
EmulatePLIRegister (ARMEncoding encoding);
|
||||
EmulatePLIRegister (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.141 RSB (immediate)
|
||||
bool
|
||||
EmulateRSBImm (ARMEncoding encoding);
|
||||
EmulateRSBImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.142 RSB (register)
|
||||
bool
|
||||
EmulateRSBReg (ARMEncoding encoding);
|
||||
EmulateRSBReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.144 RSC (immediate)
|
||||
bool
|
||||
EmulateRSCImm (ARMEncoding encoding);
|
||||
EmulateRSCImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.145 RSC (register)
|
||||
bool
|
||||
EmulateRSCReg (ARMEncoding encoding);
|
||||
EmulateRSCReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.150 SBC (immediate)
|
||||
bool
|
||||
EmulateSBCImm (ARMEncoding encoding);
|
||||
EmulateSBCImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.151 SBC (register)
|
||||
bool
|
||||
EmulateSBCReg (ARMEncoding encoding);
|
||||
EmulateSBCReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.211 SUB (immediate, Thumb)
|
||||
bool
|
||||
EmulateSUBImmThumb (ARMEncoding encoding);
|
||||
EmulateSUBImmThumb (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.212 SUB (immediate, ARM)
|
||||
bool
|
||||
EmulateSUBImmARM (ARMEncoding encoding);
|
||||
EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.222 SXTB - Encoding T1
|
||||
bool
|
||||
EmulateSXTB (ARMEncoding encoding);
|
||||
EmulateSXTB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.224 SXTH - EncodingT1
|
||||
bool
|
||||
EmulateSXTH (ARMEncoding encoding);
|
||||
EmulateSXTH (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.227 TEQ (immediate) - Encoding A1
|
||||
bool
|
||||
EmulateTEQImm (ARMEncoding encoding);
|
||||
EmulateTEQImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.228 TEQ (register) - Encoding A1
|
||||
bool
|
||||
EmulateTEQReg (ARMEncoding encoding);
|
||||
EmulateTEQReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.230 TST (immediate) - Encoding A1
|
||||
bool
|
||||
EmulateTSTImm (ARMEncoding encoding);
|
||||
EmulateTSTImm (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.231 TST (register) - Encoding T1, A1
|
||||
bool
|
||||
EmulateTSTReg (ARMEncoding encoding);
|
||||
EmulateTSTReg (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.262 UXTB - Encoding T1
|
||||
bool
|
||||
EmulateUXTB (ARMEncoding encoding);
|
||||
EmulateUXTB (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// A8.6.264 UXTH - Encoding T1
|
||||
bool
|
||||
EmulateUXTH (ARMEncoding encoding);
|
||||
EmulateUXTH (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
// B6.1.8 RFE
|
||||
bool
|
||||
EmulateRFE (ARMEncoding encoding);
|
||||
EmulateRFE (const uint32_t opcode, const ARMEncoding encoding);
|
||||
|
||||
uint32_t m_arm_isa;
|
||||
Mode m_opcode_mode;
|
||||
|
|
|
|||
Loading…
Reference in New Issue