[GlobalISel][AArch64] Legalize/select G_(S/Z/ANY)_EXT for v8s8s
This adds legalization for G_SEXT, G_ZEXT, and G_ANYEXT for v8s8s. We were falling back on G_ZEXT in arm64-vabs.ll before, preventing us from selecting the @llvm.aarch64.neon.sabd.v8i8 intrinsic. This adds legalizer support for those 3, which gives us selection via the importer. Update the relevant tests (legalize-ext.mir, select-int-ext.mir) and add a GISel line to arm64-vabs.ll. Differential Revision: https://reviews.llvm.org/D60881 llvm-svn: 358715
This commit is contained in:
Jessica Paquette
parent
3b5119c684
commit
0aa9b453c4
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@ -316,7 +316,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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// Extensions
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getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
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.legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32});
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.legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32})
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.legalFor({v8s16, v8s8});
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getActionDefinitionsBuilder(G_TRUNC).alwaysLegal();
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@ -169,3 +169,61 @@ body: |
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$w0 = COPY %3(s32)
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...
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---
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name: test_zext_v8s16_from_v8s8
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_zext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
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; CHECK: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
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; CHECK: $q0 = COPY [[ZEXT]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%1:fpr(<8 x s8>) = COPY $d0
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%2:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_sext_v8s16_from_v8s8
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_sext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
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; CHECK: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
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; CHECK: $q0 = COPY [[SEXT]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%1:fpr(<8 x s8>) = COPY $d0
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%2:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_anyext_v8s16_from_v8s8
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_anyext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
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; CHECK: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
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; CHECK: $q0 = COPY [[ANYEXT]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%1:fpr(<8 x s8>) = COPY $d0
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%2:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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@ -6,16 +6,19 @@
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define void @anyext_s64_from_s32() { ret void }
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define void @anyext_s32_from_s8() { ret void }
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define void @anyext_v8s16_from_v8s8() { ret void }
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define void @zext_s64_from_s32() { ret void }
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define void @zext_s32_from_s16() { ret void }
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define void @zext_s32_from_s8() { ret void }
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define void @zext_s16_from_s8() { ret void }
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define void @zext_v8s16_from_v8s8() { ret void }
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define void @sext_s64_from_s32() { ret void }
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define void @sext_s32_from_s16() { ret void }
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define void @sext_s32_from_s8() { ret void }
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define void @sext_s16_from_s8() { ret void }
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define void @sext_v8s16_from_v8s8() { ret void }
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...
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---
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@ -63,6 +66,31 @@ body: |
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$w0 = COPY %1(s32)
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...
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---
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name: anyext_v8s16_from_v8s8
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: anyext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv8i8_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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---
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name: zext_s64_from_s32
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legalized: true
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@ -157,6 +185,33 @@ body: |
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$w0 = COPY %3(s32)
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...
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---
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name: zext_v8s16_from_v8s8
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: zext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv8i8_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: sext_s64_from_s32
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legalized: true
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@ -250,3 +305,30 @@ body: |
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%3:gpr(s32) = G_ANYEXT %1
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$w0 = COPY %3(s32)
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...
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---
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name: sext_v8s16_from_v8s8
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: sext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[SSHLLv8i8_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s16>) = G_SEXT %0(<8 x s8>)
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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@ -1,9 +1,13 @@
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
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; FALLBACK-NOT: remark:{{.*}}(<8 x s16>) = G_ZEXT %4:_(<8 x s8>)
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; FALLBACK-NOT: remark:{{.*}} sabdl8h
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define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: sabdl8h:
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;CHECK: sabdl.8h
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;GISEL-LABEL: sabdl8h:
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;GISEL: sabdl.8h
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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