ARM assmebler parsing for two-operand VMUL instructions.
Combined destination and first source operand for f32 variant of the VMUL (by scalar) instruction. rdar://10522016 llvm-svn: 145842
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@ -231,6 +231,8 @@ class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
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class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
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class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction templates.
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@ -3672,6 +3672,15 @@ def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
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def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
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v2f32, fmul>;
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// Two-operand aliases.
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def : NEONInstAlias<"vmul${p}.f32 $Ddn $Dm$lane",
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(VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
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VectorIndex32:$lane, pred:$p)>;
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def : NEONInstAlias<"vmul${p}.f32 $Qdn $Dm$lane",
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(VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
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VectorIndex32:$lane, pred:$p)>;
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def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
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(v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
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(v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
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