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[mips] Use PredicateControl for the MSA ASE instructions. NFC. 

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13092

llvm-svn: 248486
This commit is contained in:
Daniel Sanders 2015-09-24 12:10:23 +00:00
parent 2d0ece960f
commit 090f6e41c4
3 changed files with 23 additions and 22 deletions
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11
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -208,6 +208,9 @@ def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
def HasEVA : Predicate<"Subtarget->hasEVA()">,
AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
def HasMSA : Predicate<"Subtarget->hasMSA()">,
AssemblerPredicate<"FeatureMSA">;
//===----------------------------------------------------------------------===//
// Mips GPR size adjectives.
@ -300,6 +303,14 @@ class INSN_MIPS5_32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
}
class ASE_MSA {
list<Predicate> InsnPredicates = [HasMSA];
}
class ASE_MSA64 {
list<Predicate> InsnPredicates = [HasMSA, HasMips64];
}
// Class used for separating microMIPSr6 and microMIPS (r3) instruction.
// It can be used only on instructions that doesn't inherit PredicateControl.
class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {

24
llvm/lib/Target/Mips/MipsMSAInstrFormats.td
View File

@ -7,18 +7,12 @@
//
//===----------------------------------------------------------------------===//
def HasMSA : Predicate<"Subtarget->hasMSA()">,
AssemblerPredicate<"FeatureMSA">;
class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
let Predicates = [HasMSA];
class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
PredicateControl, ASE_MSA {
let EncodingPredicates = [HasStdEnc];
let Inst{31-26} = 0b011110;
}
class MSA64Inst : MSAInst {
let Predicates = [HasMSA, HasMips64];
}
class MSACBranch : MSAInst {
let Inst{31-26} = 0b010001;
}
@ -27,10 +21,6 @@ class MSASpecial : MSAInst {
let Inst{31-26} = 0b000000;
}
class MSA64Special : MSA64Inst {
let Inst{31-26} = 0b000000;
}
class MSAPseudo<dag outs, dag ins, list<dag> pattern,
InstrItinClass itin = IIPseudo>:
MipsPseudo<outs, ins, pattern, itin> {
@ -100,7 +90,7 @@ class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
let Inst{5-0} = minor;
}
class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSA64Inst {
class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
bits<5> rs;
bits<5> wd;
@ -293,7 +283,7 @@ class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
let Inst{5-0} = minor;
}
class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
bits<4> n;
bits<5> ws;
bits<5> rd;
@ -345,7 +335,7 @@ class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
let Inst{5-0} = minor;
}
class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
bits<6> n;
bits<5> rs;
bits<5> wd;
@ -450,7 +440,7 @@ class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial {
let Inst{5-0} = minor;
}
class SPECIAL_DLSA_FMT<bits<6> minor>: MSA64Special {
class SPECIAL_DLSA_FMT<bits<6> minor>: MSASpecial {
bits<5> rs;
bits<5> rt;
bits<5> rd;

10
llvm/lib/Target/Mips/MipsMSAInstrInfo.td
View File

@ -2991,12 +2991,12 @@ def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC;
def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC;
def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC, ASE_MSA64;
def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
@ -3108,7 +3108,7 @@ def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
def FILL_B : FILL_B_ENC, FILL_B_DESC;
def FILL_H : FILL_H_ENC, FILL_H_DESC;
def FILL_W : FILL_W_ENC, FILL_W_DESC;
def FILL_D : FILL_D_ENC, FILL_D_DESC;
def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64;
def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
@ -3238,7 +3238,7 @@ def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
def INSERT_D : INSERT_D_ENC, INSERT_D_DESC;
def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64;
// INSERT_FW_PSEUDO defined after INSVE_W
// INSERT_FD_PSEUDO defined after INSVE_D
@ -3280,7 +3280,7 @@ def LDI_W : LDI_W_ENC, LDI_W_DESC;
def LDI_D : LDI_D_ENC, LDI_D_DESC;
def LSA : LSA_ENC, LSA_DESC;
def DLSA : DLSA_ENC, DLSA_DESC;
def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64;
def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;