R600/SI: Only select cvt_flr/cvt_rpi with no NaNs.
These have different behavior from cvt_i32_f32 on NaN. llvm-svn: 227693
This commit is contained in:
Matt Arsenault
parent
3475dc358c
commit
08ad328ae2
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@ -612,12 +612,14 @@ def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
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def cvt_rpi_i32_f32 : PatFrag <
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(ops node:$src),
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(fp_to_sint (ffloor (fadd $src, FP_HALF)))
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(fp_to_sint (ffloor (fadd $src, FP_HALF))),
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[{ (void) N; return TM.Options.NoNaNsFPMath; }]
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>;
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def cvt_flr_i32_f32 : PatFrag <
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(ops node:$src),
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(fp_to_sint (ffloor $src))
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(fp_to_sint (ffloor $src)),
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[{ (void)N; return TM.Options.NoNaNsFPMath; }]
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>;
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/*
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@ -1,12 +1,14 @@
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; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.fabs.f32(float) #1
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declare float @llvm.floor.f32(float) #1
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_0:
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NOT: add
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; SI: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; SI: s_endpgm
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define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
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%floor = call float @llvm.floor.f32(float %x) #1
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@ -17,7 +19,8 @@ define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1:
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; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}}
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; SI: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
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; SI: s_endpgm
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define void @cvt_flr_i32_f32_1(i32 addrspace(1)* %out, float %x) #0 {
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%fadd = fadd float %x, 1.0
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@ -29,7 +32,8 @@ define void @cvt_flr_i32_f32_1(i32 addrspace(1)* %out, float %x) #0 {
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs:
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; SI-NOT: add
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; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
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; SI: s_endpgm
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define void @cvt_flr_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
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%x.fabs = call float @llvm.fabs.f32(float %x) #1
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@ -41,7 +45,8 @@ define void @cvt_flr_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fneg:
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; SI-NOT: add
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; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
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; SI: s_endpgm
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define void @cvt_flr_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
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%x.fneg = fsub float -0.000000e+00, %x
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@ -53,7 +58,8 @@ define void @cvt_flr_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs_fneg:
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; SI-NOT: add
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; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
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; SI: s_endpgm
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define void @cvt_flr_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
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%x.fabs = call float @llvm.fabs.f32(float %x) #1
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@ -1,11 +1,13 @@
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; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.fabs.f32(float) #1
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declare float @llvm.floor.f32(float) #1
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; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:
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; SI: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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; SI-NONAN: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; SI: s_endpgm
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define void @cvt_rpi_i32_f32(i32 addrspace(1)* %out, float %x) #0 {
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%fadd = fadd float %x, 0.5
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@ -16,7 +18,8 @@ define void @cvt_rpi_i32_f32(i32 addrspace(1)* %out, float %x) #0 {
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}
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; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:
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; SI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
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; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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; SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
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; SI: s_endpgm
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define void @cvt_rpi_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
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%x.fabs = call float @llvm.fabs.f32(float %x) #1
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@ -29,9 +32,10 @@ define void @cvt_rpi_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
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; FIXME: This doesn't work because it forms fsub 0.5, x
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; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:
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; XSI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
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; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
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; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}
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; SI: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
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; SI: s_endpgm
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define void @cvt_rpi_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
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%x.fneg = fsub float -0.000000e+00, %x
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@ -44,10 +48,12 @@ define void @cvt_rpi_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
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; FIXME: This doesn't work for same reason as above
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; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:
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; XSI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
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; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
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; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|
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; SI: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
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; SI: s_endpgm
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define void @cvt_rpi_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
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%x.fabs = call float @llvm.fabs.f32(float %x) #1
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