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d1bee6ee12
commit
085663c4ec
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@ -134,7 +134,6 @@ namespace {
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printMemReference(MI, OpNo);
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printMemReference(MI, OpNo);
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}
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}
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bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC);
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void printMachineInstruction(const MachineInstr *MI);
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
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void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
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void printMemReference(const MachineInstr *MI, unsigned Op);
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void printMemReference(const MachineInstr *MI, unsigned Op);
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@ -541,37 +540,6 @@ void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
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O << "]";
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O << "]";
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}
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}
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/// printImplUsesAfter - Emit the implicit-use registers for the instruction
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/// described by DESC, if its PrintImplUsesAfter flag is set.
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///
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/// Inputs:
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/// Comma - List of registers will need a leading comma.
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/// Desc - Description of the Instruction.
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///
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/// Return value:
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/// true - Emitted one or more registers.
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/// false - Emitted no registers.
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///
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bool X86AsmPrinter::printImplUsesAfter(const TargetInstrDescriptor &Desc,
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const bool Comma = true) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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if (Desc.TSFlags & X86II::PrintImplUsesAfter) {
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bool emitted = false;
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const unsigned *p = Desc.ImplicitUses;
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if (*p) {
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O << (Comma ? ", %" : "%") << RI.get (*p).Name;
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emitted = true;
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++p;
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}
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while (*p) {
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// Bug Workaround: See note in X86AsmPrinter::doInitialization about %.
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O << ", %" << RI.get(*p).Name;
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++p;
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}
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return emitted;
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}
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return false;
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}
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/// printMachineInstruction -- Print out a single X86 LLVM instruction
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/// printMachineInstruction -- Print out a single X86 LLVM instruction
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/// MI in Intel syntax to the current output stream.
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/// MI in Intel syntax to the current output stream.
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