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Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 

llvm-svn: 192090
This commit is contained in:
Craig Topper 2013-10-07 07:19:47 +00:00
parent 68d2546ec6
commit 07ad1b23bb
4 changed files with 14 additions and 13 deletions
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12
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -4774,18 +4774,6 @@ def VMOVQd64rr_alt : VS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
IIC_SSE_MOVDQ>, VEX, VEX_W;
} // SchedRW
// Instructions for the disassembler
// xr = XMM register
// xm = mem64
let SchedRW = [WriteMove] in {
let Predicates = [UseAVX] in
def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
} // SchedRW
//===---------------------------------------------------------------------===//
// SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
//===---------------------------------------------------------------------===//

6
llvm/test/MC/Disassembler/X86/x86-32.txt
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@ -690,3 +690,9 @@
# CHECK: decl %ecx
0x49
# CHECK: movq %xmm0, %xmm0
0xf3 0x0f 0x7e 0xc0
# CHECK: vmovq %xmm0, %xmm0
0xc5 0xfa 0x7e 0xc0

6
llvm/test/MC/Disassembler/X86/x86-64.txt
View File

@ -223,3 +223,9 @@
# CHECK: decq %rcx
0x48 0xff 0xc9
# CHECK: movq %xmm0, %xmm0
0xf3 0x0f 0x7e 0xc0
# CHECK: vmovq %xmm0, %xmm0
0xc5 0xfa 0x7e 0xc0

3
llvm/utils/TableGen/X86RecognizableInstr.cpp
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@ -538,7 +538,8 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
return FILTER_WEAK;
if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos &&
Name != "MOVZPQILo2PQIrr")
return FILTER_WEAK;
if (Name.find("Fs") != Name.npos)
return FILTER_WEAK;