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[TableGen] Emit more variant transitions 

`llvm-mca` relies on the predicates to be based on `MCSchedPredicate` in order
to resolve the scheduling for variant instructions.  Otherwise, it aborts
the building of the instruction model early.

However, the scheduling model emitter in `TableGen` gives up too soon, unless
all processors use only such predicates.

In order to allow more processors to be used with `llvm-mca`, this patch
emits scheduling transitions if any processor uses these predicates.  The
transition emitted for the processors using legacy predicates is the one
specified with `NoSchedPred`, which is based on `MCSchedPredicate`.

Preferably, `llvm-mca` should instead assume a reasonable default when a
variant transition is not based on `MCSchedPredicate` for a given processor.
This issue should be revisited in the future.

Differential revision: https://reviews.llvm.org/D54648

llvm-svn: 347504
This commit is contained in:
Evandro Menezes 2018-11-23 21:17:33 +00:00
parent 7e32cc8353
commit 079bf4b7b4
5 changed files with 67 additions and 10 deletions
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4
llvm/include/llvm/Target/TargetSchedule.td
View File

@ -373,6 +373,10 @@ class SchedPredicate<code pred> : SchedPredicateBase {
SchedMachineModel SchedModel = ?;
code Predicate = pred;
}
// Define a predicate to be typically used as the default case in a
// SchedVariant. It the SchedVariant does not use any other predicate based on
// MCSchedPredicate, this is the default scheduling case used by llvm-mca.
def NoSchedPred : MCSchedPredicate<TruePred>;
// Associate a predicate with a list of SchedReadWrites. By default,

26
llvm/test/tools/llvm-mca/AArch64/CortexA57/shifted-register.s
View File

@ -1,7 +1,25 @@
# RUN: not llvm-mca -march=aarch64 -mcpu=cortex-a57 -resource-pressure=false < %s 2> %t
# RUN: FileCheck --input-file %t %s
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -march=aarch64 -mcpu=cortex-a57 -resource-pressure=false < %s | FileCheck %s
add x0, x1, x2, lsl #3
# CHECK: error
# CHECK-SAME: unable to resolve scheduling class for write variant.
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 100
# CHECK-NEXT: Total Cycles: 53
# CHECK-NEXT: Total uOps: 100
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 1.89
# CHECK-NEXT: IPC: 1.89
# CHECK-NEXT: Block RThroughput: 0.5
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 0.50 add x0, x1, x2, lsl #3

28
llvm/test/tools/llvm-mca/AArch64/Cyclone/register-offset.s
View File

@ -1,9 +1,29 @@
# RUN: not llvm-mca -march=aarch64 -mcpu=cyclone -resource-pressure=false < %s 2> %t
# RUN: FileCheck --input-file %t %s
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -march=aarch64 -mcpu=cyclone -resource-pressure=false < %s | FileCheck %s
ldr x7, [x1, #8]
ldr x6, [x1, x2]
ldr x4, [x1, x2, sxtx]
# CHECK: error
# CHECK-SAME: unable to resolve scheduling class for write variant.
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 300
# CHECK-NEXT: Total Cycles: 156
# CHECK-NEXT: Total uOps: 300
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 1.92
# CHECK-NEXT: IPC: 1.92
# CHECK-NEXT: Block RThroughput: 1.5
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 0.50 * ldr x7, [x1, #8]
# CHECK-NEXT: 1 4 0.50 * ldr x6, [x1, x2]
# CHECK-NEXT: 1 4 0.50 * ldr x4, [x1, x2, sxtx]

2
llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s
View File

@ -1,4 +1,6 @@
# RUN: not llvm-mca -march=arm -mcpu=swift -all-views=false 2>&1 < %s | FileCheck %s
# D54648 results in this test to become valid.
# XFAIL: *
add r3, r1, r12, lsl #2

17
llvm/utils/TableGen/SubtargetEmitter.cpp
View File

@ -1504,9 +1504,9 @@ void collectVariantClasses(const CodeGenSchedModels &SchedModels,
continue;
if (OnlyExpandMCInstPredicates) {
// Ignore this variant scheduling class if transitions don't uses any
// Ignore this variant scheduling class no transitions use any meaningful
// MCSchedPredicate definitions.
if (!all_of(SC.Transitions, [](const CodeGenSchedTransition &T) {
if (!any_of(SC.Transitions, [](const CodeGenSchedTransition &T) {
return hasMCSchedPredicates(T);
}))
continue;
@ -1560,6 +1560,7 @@ void SubtargetEmitter::emitSchedModelHelpersImpl(
PE.setExpandForMC(OnlyExpandMCInstPredicates);
for (unsigned PI : ProcIndices) {
OS << " ";
// Emit a guard on the processor ID.
if (PI != 0) {
OS << (OnlyExpandMCInstPredicates
@ -1573,11 +1574,23 @@ void SubtargetEmitter::emitSchedModelHelpersImpl(
for (const CodeGenSchedTransition &T : SC.Transitions) {
if (PI != 0 && !count(T.ProcIndices, PI))
continue;
// Emit only transitions based on MCSchedPredicate, if it's the case.
// At least the transition specified by NoSchedPred is emitted,
// which becomes the default transition for those variants otherwise
// not based on MCSchedPredicate.
// FIXME: preferably, llvm-mca should instead assume a reasonable
// default when a variant transition is not based on MCSchedPredicate
// for a given processor.
if (OnlyExpandMCInstPredicates && !hasMCSchedPredicates(T))
continue;
PE.setIndentLevel(3);
emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);
}
OS << " }\n";
if (PI == 0)
break;
}