Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. llvm-svn: 118201
This commit is contained in:
Owen Anderson
parent
f211510ff6
commit
0747307049
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@ -101,6 +101,7 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
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setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
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setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
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setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
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for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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@ -820,6 +821,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::FMAX: return "ARMISD::FMAX";
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case ARMISD::FMIN: return "ARMISD::FMIN";
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case ARMISD::BFI: return "ARMISD::BFI";
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case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
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}
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}
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@ -3431,6 +3433,32 @@ static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue LowerOR(SDValue Op, SelectionDAG &DAG) {
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SDValue Op1 = Op.getOperand(1);
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while (Op1.getOpcode() == ISD::BIT_CONVERT && Op1.getOperand(0) != Op1)
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Op1 = Op1.getOperand(0);
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if (Op1.getOpcode() != ARMISD::VMOVIMM) return Op;
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ConstantSDNode* TargetConstant = cast<ConstantSDNode>(Op1.getOperand(0));
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uint32_t ConstVal = TargetConstant->getZExtValue();
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// FIXME: VORRIMM only supports immediate encodings of 16 and 32 bit size.
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// In theory for VMOVIMMs whose value is already encoded as with an
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// 8 bit encoding, we could re-encode it as a 16 or 32 bit immediate.
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EVT VorrVT = Op1.getValueType();
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EVT EltVT = VorrVT.getVectorElementType();
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if (EltVT != MVT::i16 && EltVT != MVT::i32) return Op;
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ConstVal |= 0x0100;
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SDValue OrConst = DAG.getTargetConstant(ConstVal, MVT::i32);
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DebugLoc dl = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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SDValue toTy = DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, Op.getOperand(0));
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SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, toTy, OrConst);
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return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr);
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}
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// If this is a case we can't handle, return null and let the default
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// expansion code take care of it.
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static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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@ -3899,6 +3927,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
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case ISD::MUL: return LowerMUL(Op, DAG);
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case ISD::OR: return LowerOR(Op, DAG);
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}
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return SDValue();
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}
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@ -162,7 +162,10 @@ namespace llvm {
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FMIN,
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// Bit-field insert
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BFI
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BFI,
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// Vector OR with immediate
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VORRIMM
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};
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}
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@ -69,6 +69,10 @@ def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
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def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
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def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
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def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, i32>]>;
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def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
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def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
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// VDUPLANE can produce a quad-register result from a double-register source,
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@ -3295,6 +3299,43 @@ def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
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def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
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v4i32, v4i32, or, 1>;
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def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
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(outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
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IIC_VMOVImm,
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"vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
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[(set DPR:$Vd,
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(v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
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let Inst{9} = SIMM{9};
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}
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def VORRiv2i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 0, 0, 1,
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(outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
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IIC_VMOVImm,
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"vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
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[(set DPR:$Vd,
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(v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
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let Inst{11-9} = SIMM{11-9};
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}
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def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
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(outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
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IIC_VMOVImm,
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"vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
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[(set QPR:$Vd,
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(v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
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let Inst{9} = SIMM{9};
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}
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def VORRiv4i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 1, 0, 1,
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(outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
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IIC_VMOVImm,
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"vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
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[(set QPR:$Vd,
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(v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
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let Inst{11-9} = SIMM{11-9};
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}
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// VBIC : Vector Bitwise Bit Clear (AND NOT)
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def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
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(ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
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@ -505,3 +505,23 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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%tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
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ret <4 x i32> %tmp5
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}
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define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
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; CHECK: v_orrimm:
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; CHECK-NOT: vmov
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; CHECK-NOT: vmvn
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; CHECK: vorr
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%tmp1 = load <8 x i8>* %A
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%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
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; CHECK: v_orrimmQ
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; CHECK-NOT: vmov
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; CHECK-NOT: vmvn
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; CHECK: vorr
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%tmp1 = load <16 x i8>* %A
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%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
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ret <16 x i8> %tmp3
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}
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@ -1,4 +1,5 @@
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@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
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@ XFAIL: *
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@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2]
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vand d16, d17, d16
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@ -14,6 +15,10 @@
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vorr d16, d17, d16
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@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2]
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vorr q8, q8, q9
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@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2]
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vorr.i32 d16, #0x1000000
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@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2]
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vorr.i32 q8, #0x1000000
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@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2]
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vbic d16, d17, d16
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