replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[SelectionDAG] GetDemandedBits - cleanup to more closely match SimplifyDemandedBits. NFCI. 

Prep work before adding demanded elts support.

llvm-svn: 361739
This commit is contained in:
Simon Pilgrim 2019-05-26 18:58:14 +00:00
parent 2916b9e28c
commit 06e02856ab
1 changed files with 21 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2123,15 +2123,17 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
/// See if the specified operand can be simplified with the knowledge that only
/// the bits specified by Mask are used.
SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &Mask) {
/// TODO: really we should be making this into the DAG equivalent of
/// SimplifyMultipleUseDemandedBits and not generate any new nodes.
SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &DemandedBits) {
switch (V.getOpcode()) {
default:
break;
case ISD::Constant: {
const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
auto *CV = cast<ConstantSDNode>(V.getNode());
assert(CV && "Const value should be ConstSDNode.");
const APInt &CVal = CV->getAPIntValue();
APInt NewVal = CVal & Mask;
APInt NewVal = CVal & DemandedBits;
if (NewVal != CVal)
return getConstant(NewVal, SDLoc(V), V.getValueType());
break;
@ -2139,24 +2141,25 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &Mask) {
case ISD::OR:
case ISD::XOR:
// If the LHS or RHS don't contribute bits to the or, drop them.
if (MaskedValueIsZero(V.getOperand(0), Mask))
if (MaskedValueIsZero(V.getOperand(0), DemandedBits))
return V.getOperand(1);
if (MaskedValueIsZero(V.getOperand(1), Mask))
if (MaskedValueIsZero(V.getOperand(1), DemandedBits))
return V.getOperand(0);
break;
case ISD::SRL:
// Only look at single-use SRLs.
if (!V.getNode()->hasOneUse())
break;
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
if (auto *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
// See if we can recursively simplify the LHS.
unsigned Amt = RHSC->getZExtValue();
// Watch out for shift count overflow though.
if (Amt >= Mask.getBitWidth())
if (Amt >= DemandedBits.getBitWidth())
break;
APInt NewMask = Mask << Amt;
if (SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask))
APInt SrcDemandedBits = DemandedBits << Amt;
if (SDValue SimplifyLHS =
GetDemandedBits(V.getOperand(0), SrcDemandedBits))
return getNode(ISD::SRL, SDLoc(V), V.getValueType(), SimplifyLHS,
V.getOperand(1));
}
@ -2166,8 +2169,9 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &Mask) {
// Also handle the case where masked out bits in X are known to be zero.
if (ConstantSDNode *RHSC = isConstOrConstSplat(V.getOperand(1))) {
const APInt &AndVal = RHSC->getAPIntValue();
if (Mask.isSubsetOf(AndVal) ||
Mask.isSubsetOf(computeKnownBits(V.getOperand(0)).Zero | AndVal))
if (DemandedBits.isSubsetOf(AndVal) ||
DemandedBits.isSubsetOf(computeKnownBits(V.getOperand(0)).Zero |
AndVal))
return V.getOperand(0);
}
break;
@ -2176,11 +2180,12 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &Mask) {
SDValue Src = V.getOperand(0);
unsigned SrcBitWidth = Src.getScalarValueSizeInBits();
// Being conservative here - only peek through if we only demand bits in the
// non-extended source (even though the extended bits are technically undef).
if (Mask.getActiveBits() > SrcBitWidth)
// non-extended source (even though the extended bits are technically
// undef).
if (DemandedBits.getActiveBits() > SrcBitWidth)
break;
APInt SrcMask = Mask.trunc(SrcBitWidth);
if (SDValue DemandedSrc = GetDemandedBits(Src, SrcMask))
APInt SrcDemandedBits = DemandedBits.trunc(SrcBitWidth);
if (SDValue DemandedSrc = GetDemandedBits(Src, SrcDemandedBits))
return getNode(ISD::ANY_EXTEND, SDLoc(V), V.getValueType(), DemandedSrc);
break;
}
@ -2189,7 +2194,7 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &Mask) {
unsigned ExVTBits = ExVT.getScalarSizeInBits();
// If none of the extended bits are demanded, eliminate the sextinreg.
if (Mask.getActiveBits() <= ExVTBits)
if (DemandedBits.getActiveBits() <= ExVTBits)
return V.getOperand(0);
break;