ARM: Fix more fast-isel verifier failures.
Teach the generic instruction selection helper functions to constrain the register classes of their input operands. For non-physical register references, the generic code needs to be careful not to mess that up when replacing references to result registers. As the comment indicates for MachineRegisterInfo::replaceRegWith(), it's important to call constrainRegClass() first. rdar://12594152 llvm-svn: 188593
This commit is contained in:
parent
d69f3ed947
commit
06c2a68125
|
@ -497,6 +497,10 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
|
||||||
if (J == E) break;
|
if (J == E) break;
|
||||||
To = J->second;
|
To = J->second;
|
||||||
}
|
}
|
||||||
|
// Make sure the new register has a sufficiently constrained register class.
|
||||||
|
if (TargetRegisterInfo::isVirtualRegister(From) &&
|
||||||
|
TargetRegisterInfo::isVirtualRegister(To))
|
||||||
|
MRI.constrainRegClass(To, MRI.getRegClass(From));
|
||||||
// Replace it.
|
// Replace it.
|
||||||
MRI.replaceRegWith(From, To);
|
MRI.replaceRegWith(From, To);
|
||||||
}
|
}
|
||||||
|
|
|
@ -176,6 +176,8 @@ class ARMFastISel : public FastISel {
|
||||||
|
|
||||||
// Utility routines.
|
// Utility routines.
|
||||||
private:
|
private:
|
||||||
|
unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned OpNum,
|
||||||
|
unsigned Op);
|
||||||
bool isTypeLegal(Type *Ty, MVT &VT);
|
bool isTypeLegal(Type *Ty, MVT &VT);
|
||||||
bool isLoadTypeLegal(Type *Ty, MVT &VT);
|
bool isLoadTypeLegal(Type *Ty, MVT &VT);
|
||||||
bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
|
bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
|
||||||
|
@ -291,6 +293,23 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
|
||||||
return MIB;
|
return MIB;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
unsigned ARMFastISel::constrainOperandRegClass(const MCInstrDesc &II,
|
||||||
|
unsigned Op, unsigned OpNum) {
|
||||||
|
if (TargetRegisterInfo::isVirtualRegister(Op)) {
|
||||||
|
const TargetRegisterClass *RegClass =
|
||||||
|
TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
|
||||||
|
if (!MRI.constrainRegClass(Op, RegClass)) {
|
||||||
|
// If it's not legal to COPY between the register classes, something
|
||||||
|
// has gone very wrong before we got here.
|
||||||
|
unsigned NewOp = createResultReg(RegClass);
|
||||||
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
||||||
|
TII.get(TargetOpcode::COPY), NewOp).addReg(Op));
|
||||||
|
return NewOp;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return Op;
|
||||||
|
}
|
||||||
|
|
||||||
unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
|
unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
|
||||||
const TargetRegisterClass* RC) {
|
const TargetRegisterClass* RC) {
|
||||||
unsigned ResultReg = createResultReg(RC);
|
unsigned ResultReg = createResultReg(RC);
|
||||||
|
@ -306,6 +325,9 @@ unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
|
||||||
unsigned ResultReg = createResultReg(RC);
|
unsigned ResultReg = createResultReg(RC);
|
||||||
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
||||||
|
|
||||||
|
// Make sure the input operand is sufficiently constrained to be legal
|
||||||
|
// for this instruction.
|
||||||
|
Op0 = constrainOperandRegClass(II, Op0, 1);
|
||||||
if (II.getNumDefs() >= 1) {
|
if (II.getNumDefs() >= 1) {
|
||||||
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
||||||
.addReg(Op0, Op0IsKill * RegState::Kill));
|
.addReg(Op0, Op0IsKill * RegState::Kill));
|
||||||
|
@ -326,6 +348,11 @@ unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
|
||||||
unsigned ResultReg = createResultReg(RC);
|
unsigned ResultReg = createResultReg(RC);
|
||||||
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
||||||
|
|
||||||
|
// Make sure the input operands are sufficiently constrained to be legal
|
||||||
|
// for this instruction.
|
||||||
|
Op0 = constrainOperandRegClass(II, Op0, 1);
|
||||||
|
Op1 = constrainOperandRegClass(II, Op1, 2);
|
||||||
|
|
||||||
if (II.getNumDefs() >= 1) {
|
if (II.getNumDefs() >= 1) {
|
||||||
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
||||||
.addReg(Op0, Op0IsKill * RegState::Kill)
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
||||||
|
@ -349,6 +376,12 @@ unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
|
||||||
unsigned ResultReg = createResultReg(RC);
|
unsigned ResultReg = createResultReg(RC);
|
||||||
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
||||||
|
|
||||||
|
// Make sure the input operands are sufficiently constrained to be legal
|
||||||
|
// for this instruction.
|
||||||
|
Op0 = constrainOperandRegClass(II, Op0, 1);
|
||||||
|
Op1 = constrainOperandRegClass(II, Op1, 2);
|
||||||
|
Op2 = constrainOperandRegClass(II, Op1, 3);
|
||||||
|
|
||||||
if (II.getNumDefs() >= 1) {
|
if (II.getNumDefs() >= 1) {
|
||||||
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
||||||
.addReg(Op0, Op0IsKill * RegState::Kill)
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
||||||
|
@ -373,6 +406,9 @@ unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
|
||||||
unsigned ResultReg = createResultReg(RC);
|
unsigned ResultReg = createResultReg(RC);
|
||||||
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
||||||
|
|
||||||
|
// Make sure the input operand is sufficiently constrained to be legal
|
||||||
|
// for this instruction.
|
||||||
|
Op0 = constrainOperandRegClass(II, Op0, 1);
|
||||||
if (II.getNumDefs() >= 1) {
|
if (II.getNumDefs() >= 1) {
|
||||||
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
||||||
.addReg(Op0, Op0IsKill * RegState::Kill)
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
||||||
|
@ -395,6 +431,9 @@ unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
|
||||||
unsigned ResultReg = createResultReg(RC);
|
unsigned ResultReg = createResultReg(RC);
|
||||||
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
||||||
|
|
||||||
|
// Make sure the input operand is sufficiently constrained to be legal
|
||||||
|
// for this instruction.
|
||||||
|
Op0 = constrainOperandRegClass(II, Op0, 1);
|
||||||
if (II.getNumDefs() >= 1) {
|
if (II.getNumDefs() >= 1) {
|
||||||
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
||||||
.addReg(Op0, Op0IsKill * RegState::Kill)
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
||||||
|
@ -418,6 +457,10 @@ unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
|
||||||
unsigned ResultReg = createResultReg(RC);
|
unsigned ResultReg = createResultReg(RC);
|
||||||
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
||||||
|
|
||||||
|
// Make sure the input operands are sufficiently constrained to be legal
|
||||||
|
// for this instruction.
|
||||||
|
Op0 = constrainOperandRegClass(II, Op0, 1);
|
||||||
|
Op1 = constrainOperandRegClass(II, Op1, 2);
|
||||||
if (II.getNumDefs() >= 1) {
|
if (II.getNumDefs() >= 1) {
|
||||||
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
||||||
.addReg(Op0, Op0IsKill * RegState::Kill)
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
|
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
|
||||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
|
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
|
||||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
|
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
|
||||||
|
|
||||||
; Very basic fast-isel functionality.
|
; Very basic fast-isel functionality.
|
||||||
define i32 @test0(i32 %a, i32 %b) nounwind {
|
define i32 @test0(i32 %a, i32 %b) nounwind {
|
||||||
|
|
Loading…
Reference in New Issue