AMDGPU: Add num spilled s/vgprs to metadata
This was requested by tools. Differential Revision: https://reviews.llvm.org/D40321 llvm-svn: 319192
This commit is contained in:
Konstantin Zhuravlyov
parent
5011298958
commit
06ae4ec78e
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@ -1295,6 +1295,16 @@ non-AMD key names should be prefixed by "*vendor-name*.".
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code is capable of
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supporting XNACK. See
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:ref:`amdgpu-target-features`.
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"NumSpilledSGPRs" integer Number of stores from
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a scalar register to
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a register allocator
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created spill
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location.
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"NumSpilledVGPRs" integer Number of stores from
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a vector register to
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a register allocator
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created spill
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location.
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============================ ============== ========= =====================
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..
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@ -244,6 +244,10 @@ constexpr char MaxFlatWorkGroupSize[] = "MaxFlatWorkGroupSize";
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constexpr char IsDynamicCallStack[] = "IsDynamicCallStack";
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/// \brief Key for Kernel::CodeProps::Metadata::mIsXNACKEnabled.
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constexpr char IsXNACKEnabled[] = "IsXNACKEnabled";
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/// \brief Key for Kernel::CodeProps::Metadata::mNumSpilledSGPRs.
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constexpr char NumSpilledSGPRs[] = "NumSpilledSGPRs";
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/// \brief Key for Kernel::CodeProps::Metadata::mNumSpilledVGPRs.
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constexpr char NumSpilledVGPRs[] = "NumSpilledVGPRs";
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} // end namespace Key
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/// \brief In-memory representation of kernel code properties metadata.
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@ -275,6 +279,10 @@ struct Metadata final {
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/// \brief True if the generated machine code is capable of supporting XNACK.
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/// Optional.
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bool mIsXNACKEnabled = false;
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/// \brief Number of SGPRs spilled by a wavefront. Optional.
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uint16_t mNumSpilledSGPRs = 0;
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/// \brief Number of VGPRs spilled by a workitem. Optional.
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uint16_t mNumSpilledVGPRs = 0;
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/// \brief Default constructor.
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Metadata() = default;
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@ -148,6 +148,10 @@ struct MappingTraits<Kernel::CodeProps::Metadata> {
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MD.mIsDynamicCallStack, false);
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YIO.mapOptional(Kernel::CodeProps::Key::IsXNACKEnabled,
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MD.mIsXNACKEnabled, false);
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YIO.mapOptional(Kernel::CodeProps::Key::NumSpilledSGPRs,
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MD.mNumSpilledSGPRs, uint16_t(0));
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YIO.mapOptional(Kernel::CodeProps::Key::NumSpilledVGPRs,
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MD.mNumSpilledVGPRs, uint16_t(0));
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}
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};
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@ -1188,6 +1188,8 @@ AMDGPU::HSAMD::Kernel::CodeProps::Metadata AMDGPUAsmPrinter::getHSACodeProps(
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HSACodeProps.mMaxFlatWorkGroupSize = MFI.getMaxFlatWorkGroupSize();
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HSACodeProps.mIsDynamicCallStack = ProgramInfo.DynamicCallStack;
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HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled();
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HSACodeProps.mNumSpilledSGPRs = MFI.getNumSpilledSGPRs();
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HSACodeProps.mNumSpilledVGPRs = MFI.getNumSpilledVGPRs();
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return HSACodeProps;
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}
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@ -1,26 +1,26 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=NOTES %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
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@var = addrspace(1) global float 0.0
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; CHECK: ---
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; CHECK: Version: [ 1, 0 ]
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; CHECK: Kernels:
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; CHECK: - Name: test
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; CHECK: SymbolName: 'test@kd'
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; CHECK: CodeProps:
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; CHECK: KernargSegmentSize: 24
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; CHECK: GroupSegmentFixedSize: 0
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; CHECK: PrivateSegmentFixedSize: 0
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; CHECK: KernargSegmentAlign: 8
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; CHECK: WavefrontSize: 64
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; GFX700: NumSGPRs: 6
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; GFX800: NumSGPRs: 96
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; GFX900: NumSGPRs: 6
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; GFX700: NumVGPRs: 4
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; GFX800: NumVGPRs: 6
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; GFX900: NumVGPRs: 6
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; CHECK: MaxFlatWorkGroupSize: 256
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; CHECK: - Name: test
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; CHECK: SymbolName: 'test@kd'
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; CHECK: CodeProps:
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; CHECK: KernargSegmentSize: 24
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; CHECK: GroupSegmentFixedSize: 0
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; CHECK: PrivateSegmentFixedSize: 0
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; CHECK: KernargSegmentAlign: 8
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; CHECK: WavefrontSize: 64
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; CHECK: NumSGPRs: 6
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; GFX700: NumVGPRs: 4
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; GFX803: NumVGPRs: 6
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; GFX900: NumVGPRs: 6
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; CHECK: MaxFlatWorkGroupSize: 256
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define amdgpu_kernel void @test(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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@ -32,3 +32,111 @@ entry:
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; CHECK: - Name: num_spilled_sgprs
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; CHECK: SymbolName: 'num_spilled_sgprs@kd'
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; CHECK: CodeProps:
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; CHECK: NumSpilledSGPRs: 41
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define amdgpu_kernel void @num_spilled_sgprs(
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i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %out2,
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i32 addrspace(1)* %out3, i32 addrspace(1)* %out4, i32 addrspace(1)* %out5,
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i32 addrspace(1)* %out6, i32 addrspace(1)* %out7, i32 addrspace(1)* %out8,
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i32 addrspace(1)* %out9, i32 addrspace(1)* %outa, i32 addrspace(1)* %outb,
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i32 addrspace(1)* %outc, i32 addrspace(1)* %outd, i32 addrspace(1)* %oute,
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i32 addrspace(1)* %outf, i32 %in0, i32 %in1, i32 %in2, i32 %in3, i32 %in4,
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i32 %in5, i32 %in6, i32 %in7, i32 %in8, i32 %in9, i32 %ina, i32 %inb,
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i32 %inc, i32 %ind, i32 %ine, i32 %inf) #0 {
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entry:
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store i32 %in0, i32 addrspace(1)* %out0
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store i32 %in1, i32 addrspace(1)* %out1
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store i32 %in2, i32 addrspace(1)* %out2
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store i32 %in3, i32 addrspace(1)* %out3
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store i32 %in4, i32 addrspace(1)* %out4
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store i32 %in5, i32 addrspace(1)* %out5
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store i32 %in6, i32 addrspace(1)* %out6
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store i32 %in7, i32 addrspace(1)* %out7
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store i32 %in8, i32 addrspace(1)* %out8
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store i32 %in9, i32 addrspace(1)* %out9
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store i32 %ina, i32 addrspace(1)* %outa
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store i32 %inb, i32 addrspace(1)* %outb
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store i32 %inc, i32 addrspace(1)* %outc
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store i32 %ind, i32 addrspace(1)* %outd
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store i32 %ine, i32 addrspace(1)* %oute
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store i32 %inf, i32 addrspace(1)* %outf
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ret void
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}
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; CHECK: - Name: num_spilled_vgprs
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; CHECK: SymbolName: 'num_spilled_vgprs@kd'
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; CHECK: CodeProps:
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; CHECK: NumSpilledVGPRs: 14
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define amdgpu_kernel void @num_spilled_vgprs() #1 {
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%val0 = load volatile float, float addrspace(1)* @var
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%val1 = load volatile float, float addrspace(1)* @var
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%val2 = load volatile float, float addrspace(1)* @var
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%val3 = load volatile float, float addrspace(1)* @var
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%val4 = load volatile float, float addrspace(1)* @var
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%val5 = load volatile float, float addrspace(1)* @var
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%val6 = load volatile float, float addrspace(1)* @var
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%val7 = load volatile float, float addrspace(1)* @var
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%val8 = load volatile float, float addrspace(1)* @var
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%val9 = load volatile float, float addrspace(1)* @var
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%val10 = load volatile float, float addrspace(1)* @var
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%val11 = load volatile float, float addrspace(1)* @var
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%val12 = load volatile float, float addrspace(1)* @var
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%val13 = load volatile float, float addrspace(1)* @var
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%val14 = load volatile float, float addrspace(1)* @var
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%val15 = load volatile float, float addrspace(1)* @var
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%val16 = load volatile float, float addrspace(1)* @var
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%val17 = load volatile float, float addrspace(1)* @var
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%val18 = load volatile float, float addrspace(1)* @var
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%val19 = load volatile float, float addrspace(1)* @var
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%val20 = load volatile float, float addrspace(1)* @var
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%val21 = load volatile float, float addrspace(1)* @var
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%val22 = load volatile float, float addrspace(1)* @var
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%val23 = load volatile float, float addrspace(1)* @var
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%val24 = load volatile float, float addrspace(1)* @var
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%val25 = load volatile float, float addrspace(1)* @var
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%val26 = load volatile float, float addrspace(1)* @var
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%val27 = load volatile float, float addrspace(1)* @var
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%val28 = load volatile float, float addrspace(1)* @var
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%val29 = load volatile float, float addrspace(1)* @var
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%val30 = load volatile float, float addrspace(1)* @var
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store volatile float %val0, float addrspace(1)* @var
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store volatile float %val1, float addrspace(1)* @var
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store volatile float %val2, float addrspace(1)* @var
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store volatile float %val3, float addrspace(1)* @var
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store volatile float %val4, float addrspace(1)* @var
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store volatile float %val5, float addrspace(1)* @var
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store volatile float %val6, float addrspace(1)* @var
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store volatile float %val7, float addrspace(1)* @var
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store volatile float %val8, float addrspace(1)* @var
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store volatile float %val9, float addrspace(1)* @var
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store volatile float %val10, float addrspace(1)* @var
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store volatile float %val11, float addrspace(1)* @var
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store volatile float %val12, float addrspace(1)* @var
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store volatile float %val13, float addrspace(1)* @var
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store volatile float %val14, float addrspace(1)* @var
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store volatile float %val15, float addrspace(1)* @var
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store volatile float %val16, float addrspace(1)* @var
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store volatile float %val17, float addrspace(1)* @var
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store volatile float %val18, float addrspace(1)* @var
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store volatile float %val19, float addrspace(1)* @var
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store volatile float %val20, float addrspace(1)* @var
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store volatile float %val21, float addrspace(1)* @var
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store volatile float %val22, float addrspace(1)* @var
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store volatile float %val23, float addrspace(1)* @var
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store volatile float %val24, float addrspace(1)* @var
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store volatile float %val25, float addrspace(1)* @var
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store volatile float %val26, float addrspace(1)* @var
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store volatile float %val27, float addrspace(1)* @var
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store volatile float %val28, float addrspace(1)* @var
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store volatile float %val29, float addrspace(1)* @var
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store volatile float %val30, float addrspace(1)* @var
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ret void
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}
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attributes #0 = { "amdgpu-num-sgpr"="14" }
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attributes #1 = { "amdgpu-num-vgpr"="20" }
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@ -14,6 +14,8 @@
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// CHECK: KernargSegmentAlign: 16
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// CHECK: WavefrontSize: 64
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// CHECK: MaxFlatWorkGroupSize: 256
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// CHECK: NumSpilledSGPRs: 1
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// CHECK: NumSpilledVGPRs: 1
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.amd_amdgpu_hsa_metadata
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Version: [ 1, 0 ]
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Printf: [ '1:1:4:%d\n', '2:1:8:%g\n' ]
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@ -27,4 +29,6 @@
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KernargSegmentAlign: 16
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WavefrontSize: 64
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MaxFlatWorkGroupSize: 256
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NumSpilledSGPRs: 1
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NumSpilledVGPRs: 1
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.end_amd_amdgpu_hsa_metadata
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