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Do Materialize Floating Point in Mips Fast-Isel 

Summary:
Implement materialize of floating point literals in Mips Fast-Isel

Reopened version of D3659

Test Plan: simplestorefp1.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4071

llvm-svn: 210546
This commit is contained in:
Reed Kotler 2014-06-10 16:45:44 +00:00
parent fa508af0fe
commit 063d4fba36
2 changed files with 61 additions and 2 deletions
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25
llvm/lib/Target/Mips/MipsFastISel.cpp
View File

@ -167,9 +167,14 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
//
// more cases will be handled here in following patches.
//
if (VT != MVT::i32)
if (VT == MVT::i32)
EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
else if (VT == MVT::f32)
EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset);
else if (VT == MVT::f64)
EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset);
else
return false;
EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
return true;
}
@ -229,6 +234,22 @@ bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
}
unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
if (VT == MVT::f32) {
const TargetRegisterClass *RC = &Mips::FGR32RegClass;
unsigned DestReg = createResultReg(RC);
unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
return DestReg;
} else if (VT == MVT::f64) {
const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
unsigned DestReg = createResultReg(RC);
unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
unsigned TempReg2 =
Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
return DestReg;
}
return 0;
}

38
llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll Normal file
View File

@ -0,0 +1,38 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
@f = common global float 0.000000e+00, align 4
@de = common global double 0.000000e+00, align 8
; Function Attrs: nounwind
define void @f1() #0 {
entry:
store float 0x3FFA76C8C0000000, float* @f, align 4
ret void
; CHECK: .ent f1
; CHECK: lui $[[REG1:[0-9]+]], 16339
; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662
; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
; CHECK: lw $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
; CHECK: swc1 $f[[REG3]], 0($[[REG4]])
; CHECK: .end f1
}
; Function Attrs: nounwind
define void @d1() #0 {
entry:
store double 1.234567e+00, double* @de, align 8
; CHECK: .ent d1
; CHECK: lui $[[REG1a:[0-9]+]], 16371
; CHECK: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
; CHECK: lui $[[REG1b:[0-9]+]], 21403
; CHECK: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
; CHECK: mtc1 $[[REG2b]], $f[[REG3b:[0-9]+]]
; CHECK: mtc1 $[[REG2a]], $f[[REG3a:[0-9]+]]
; CHECK: sdc1 $f[[REG3b]], 0(${{[0-9]+}})
; CHECK: .end d1
ret void
}
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }