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Cache invalidation for AARCH64. Disabled for Apple for now as requested 

by Tim Northover. Written by Matt Thomas.

Differential Revision: http://llvm-reviews.chandlerc.com/D2631

llvm-svn: 200317
This commit is contained in:
Joerg Sonnenberger 2014-01-28 14:02:22 +00:00
parent 1394f2da85
commit 05d8a22cf6
1 changed files with 21 additions and 0 deletions
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21
compiler-rt/lib/clear_cache.c
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@ -38,6 +38,27 @@ void __clear_cache(void* start, void* end)
arg.len = (uintptr_t)end - (uintptr_t)start;
sysarch(ARM_SYNC_ICACHE, &arg);
#elif defined(__aarch64__) && !defined(__APPLE__)
uint64_t xstart = (uint64_t)(uintptr_t) start;
uint64_t xend = (uint64_t)(uintptr_t) end;
// Get Cache Type Info
uint64_t ctr_el0;
__asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
/*
* dc & ic instructions must use 64bit registers so we don't use
* uintptr_t in case this runs in an IPL32 environment.
*/
const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
for (uint64_t addr = xstart; addr < xend; addr += dcache_line_size)
__asm __volatile("dc cvau, %0" :: "r"(addr));
__asm __volatile("dsb ish");
const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
for (uint64_t addr = xstart; addr < xend; addr += icache_line_size)
__asm __volatile("ic ivau, %0" :: "r"(addr));
__asm __volatile("isb sy");
#else
#if __APPLE__
/* On Darwin, sys_icache_invalidate() provides this functionality */