GlobalISel: simplify MachineIRBuilder interface.
MachineIRBuilder had weird before/after and beginning/end flags for the insert point. Unfortunately the non-default means that instructions will be inserted in reverse order which is almost never what anyone wants. Really, I think we just want (like IRBuilder has) the ability to insert at any C++ iterator-style point (i.e. before any instruction or before MBB.end()). So this fixes MIRBuilders to behave like IRBuilders in this respect. llvm-svn: 288980
This commit is contained in:
Tim Northover
parent
64a055549a
commit
05cc4859ad
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@ -48,8 +48,7 @@ class MachineIRBuilder {
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/// Fields describing the insertion point.
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/// @{
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MachineBasicBlock *MBB;
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MachineInstr *MI;
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bool Before;
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MachineBasicBlock::iterator II;
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/// @}
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std::function<void(MachineInstr *)> InsertedInstr;
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@ -75,22 +74,28 @@ public:
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}
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/// Current insertion point for new instructions.
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MachineBasicBlock::iterator getInsertPt();
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MachineBasicBlock::iterator getInsertPt() {
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return II;
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}
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/// Set the insertion point before the specified position.
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/// \pre MBB must be in getMF().
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/// \pre II must be a valid iterator in MBB.
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void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II);
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/// @}
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/// Setters for the insertion point.
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/// @{
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/// Set the MachineFunction where to build instructions.
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void setMF(MachineFunction &);
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/// Set the insertion point to the beginning (\p Beginning = true) or end
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/// (\p Beginning = false) of \p MBB.
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/// Set the insertion point to the end of \p MBB.
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/// \pre \p MBB must be contained by getMF().
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void setMBB(MachineBasicBlock &MBB, bool Beginning = false);
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void setMBB(MachineBasicBlock &MBB);
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/// Set the insertion point to before (\p Before = true) or after
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/// (\p Before = false) \p MI.
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/// Set the insertion point to before MI.
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/// \pre MI must be in getMF().
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void setInstr(MachineInstr &MI, bool Before = true);
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void setInstr(MachineInstr &MI);
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/// @}
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/// Control where instructions we create are recorded (typically for
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@ -744,13 +744,18 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
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assert(PendingPHIs.empty() && "stale PHIs");
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// Setup the arguments.
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MachineBasicBlock &MBB = getOrCreateBB(F.front());
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MIRBuilder.setMBB(MBB);
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// Setup a separate basic-block for the arguments and constants, falling
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// through to the IR-level Function's entry block.
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MachineBasicBlock *EntryBB = MF.CreateMachineBasicBlock();
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MF.push_back(EntryBB);
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EntryBB->addSuccessor(&getOrCreateBB(F.front()));
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EntryBuilder.setMBB(*EntryBB);
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// Lower the actual args into this basic block.
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SmallVector<unsigned, 8> VRegArgs;
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for (const Argument &Arg: F.args())
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VRegArgs.push_back(getOrCreateVReg(Arg));
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bool Succeeded = CLI->lowerFormalArguments(MIRBuilder, F, VRegArgs);
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bool Succeeded = CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs);
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if (!Succeeded) {
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if (!TPC->isGlobalISelAbortEnabled()) {
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MIRBuilder.getMF().getProperties().set(
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@ -761,13 +766,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
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report_fatal_error("Unable to lower arguments");
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}
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// Now that we've got the ABI handling code, it's safe to set a location for
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// any Constants we find in the IR.
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if (MBB.empty())
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EntryBuilder.setMBB(MBB, /* Beginning */ true);
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else
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EntryBuilder.setInstr(MBB.back(), /* Before */ false);
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// And translate the function!
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for (const BasicBlock &BB: F) {
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MachineBasicBlock &MBB = getOrCreateBB(BB);
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// Set the insertion point of all the following translations to
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@ -27,34 +27,29 @@ void MachineIRBuilder::setMF(MachineFunction &MF) {
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this->MRI = &MF.getRegInfo();
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this->TII = MF.getSubtarget().getInstrInfo();
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this->DL = DebugLoc();
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this->MI = nullptr;
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this->II = MachineBasicBlock::iterator();
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this->InsertedInstr = nullptr;
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}
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void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) {
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void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
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this->MBB = &MBB;
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this->MI = nullptr;
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Before = Beginning;
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this->II = MBB.end();
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assert(&getMF() == MBB.getParent() &&
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"Basic block is in a different function");
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}
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void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) {
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void MachineIRBuilder::setInstr(MachineInstr &MI) {
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assert(MI.getParent() && "Instruction is not part of a basic block");
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setMBB(*MI.getParent());
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this->MI = &MI;
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this->Before = Before;
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this->II = MI.getIterator();
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}
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MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() {
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if (MI) {
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if (Before)
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return MI;
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if (!MI->getNextNode())
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return getMBB().end();
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return MI->getNextNode();
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}
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return Before ? getMBB().begin() : getMBB().end();
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void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II) {
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assert(MBB.getParent() == &getMF() &&
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"Basic block is in a different function");
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this->MBB = &MBB;
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this->II = II;
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}
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void MachineIRBuilder::recordInsertions(
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@ -200,12 +200,10 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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MachineInstrBuilder MIB = MIRBuilder.buildInstr(AArch64::RET_ReallyLR);
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assert(MIB.getInstr() && "Unable to build a return instruction?!");
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auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
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assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
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bool Success = true;
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if (VReg) {
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MIRBuilder.setInstr(*MIB.getInstr(), /* Before */ true);
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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@ -221,9 +219,11 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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});
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OutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
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return handleAssignments(MIRBuilder, AssignFn, SplitArgs, Handler);
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Success = handleAssignments(MIRBuilder, AssignFn, SplitArgs, Handler);
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}
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return true;
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MIRBuilder.insertInstr(MIB);
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return Success;
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}
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bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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@ -7,8 +7,9 @@ target triple = "aarch64--"
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; Tests for add.
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; CHECK-LABEL: name: addi64
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; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
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; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_ADD [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %x0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %x0
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@ -20,6 +21,7 @@ define i64 @addi64(i64 %arg1, i64 %arg2) {
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; CHECK-LABEL: name: muli64
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; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_MUL [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %x0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %x0
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@ -51,11 +53,13 @@ define void @allocai64() {
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; CHECK-LABEL: name: uncondbr
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; CHECK: body:
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;
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; Entry basic block.
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; CHECK: {{[0-9a-zA-Z._-]+}}:
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; ABI/constant lowering basic block.
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; CHECK: {{bb.[0-9]+}}:
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; IR-level entry basic block
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; CHECK: {{bb.[0-9]+}}:
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;
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; Make sure we have one successor and only one.
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; CHECK-NEXT: successors: %[[END:[0-9a-zA-Z._-]+]](0x80000000)
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; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
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;
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; Check that we emit the correct branch.
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; CHECK: G_BR %[[END]]
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@ -73,15 +77,18 @@ end:
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; CHECK-LABEL: name: condbr
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; CHECK: body:
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;
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; Entry basic block.
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; CHECK: {{[0-9a-zA-Z._-]+}}:
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; ABI/constant lowering basic block.
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; CHECK: {{bb.[0-9]+}}:
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; CHECK: [[ADDR:%.*]](p0) = COPY %x0
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; IR-level entry basic block
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; CHECK: {{bb.[0-9]+}}:
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;
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; Make sure we have two successors
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; CHECK-NEXT: successors: %[[TRUE:[0-9a-zA-Z._-]+]](0x40000000),
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; CHECK: %[[FALSE:[0-9a-zA-Z._-]+]](0x40000000)
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; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
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; CHECK: %[[FALSE:bb.[0-9]+]](0x40000000)
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;
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; Check that we emit the correct branch.
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; CHECK: [[ADDR:%.*]](p0) = COPY %x0
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; CHECK: [[TST:%.*]](s1) = G_LOAD [[ADDR]](p0)
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; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
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; CHECK: G_BR %[[FALSE]]
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@ -104,6 +111,7 @@ false:
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; CHECK-LABEL: name: ori64
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; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_OR [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %x0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %x0
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@ -115,6 +123,7 @@ define i64 @ori64(i64 %arg1, i64 %arg2) {
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; CHECK-LABEL: name: ori32
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_OR [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -127,6 +136,7 @@ define i32 @ori32(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: xori64
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; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_XOR [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %x0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %x0
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@ -138,6 +148,7 @@ define i64 @xori64(i64 %arg1, i64 %arg2) {
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; CHECK-LABEL: name: xori32
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_XOR [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -150,6 +161,7 @@ define i32 @xori32(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: andi64
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; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_AND [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %x0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %x0
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@ -161,6 +173,7 @@ define i64 @andi64(i64 %arg1, i64 %arg2) {
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; CHECK-LABEL: name: andi32
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_AND [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -173,6 +186,7 @@ define i32 @andi32(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: subi64
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; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_SUB [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %x0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %x0
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@ -184,6 +198,7 @@ define i64 @subi64(i64 %arg1, i64 %arg2) {
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; CHECK-LABEL: name: subi32
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SUB [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -383,8 +398,8 @@ next:
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}
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; CHECK-LABEL: name: constant_int_start
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; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
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; CHECK: [[TWO:%[0-9]+]](s32) = G_CONSTANT i32 2
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; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
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; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[TWO]], [[ANSWER]]
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define i32 @constant_int_start() {
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%res = add i32 2, 42
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@ -436,6 +451,7 @@ define i64 @test_zext(i32 %in) {
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; CHECK-LABEL: name: test_shl
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SHL [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -448,6 +464,7 @@ define i32 @test_shl(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: test_lshr
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_LSHR [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -459,6 +476,7 @@ define i32 @test_lshr(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: test_ashr
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_ASHR [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -470,6 +488,7 @@ define i32 @test_ashr(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: test_sdiv
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SDIV [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -481,6 +500,7 @@ define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: test_udiv
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UDIV [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -492,6 +512,7 @@ define i32 @test_udiv(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: test_srem
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
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; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SREM [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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@ -503,6 +524,7 @@ define i32 @test_srem(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: test_urem
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: bb.1:
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UREM [[ARG1]], [[ARG2]]
|
||||
; CHECK-NEXT: %w0 = COPY [[RES]]
|
||||
; CHECK-NEXT: RET_ReallyLR implicit %w0
|
||||
|
|
@ -554,6 +576,7 @@ define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
|
|||
; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x0
|
||||
; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x1
|
||||
; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
|
||||
; CHECK: bb.1:
|
||||
; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
|
||||
; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
|
||||
define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
|
||||
|
|
@ -565,6 +588,7 @@ define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
|
|||
; CHECK-LABEL: name: test_fadd
|
||||
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
|
||||
; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
|
||||
; CHECK: bb.1:
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FADD [[ARG1]], [[ARG2]]
|
||||
; CHECK-NEXT: %s0 = COPY [[RES]]
|
||||
; CHECK-NEXT: RET_ReallyLR implicit %s0
|
||||
|
|
@ -576,6 +600,7 @@ define float @test_fadd(float %arg1, float %arg2) {
|
|||
; CHECK-LABEL: name: test_fsub
|
||||
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
|
||||
; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
|
||||
; CHECK: bb.1:
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FSUB [[ARG1]], [[ARG2]]
|
||||
; CHECK-NEXT: %s0 = COPY [[RES]]
|
||||
; CHECK-NEXT: RET_ReallyLR implicit %s0
|
||||
|
|
@ -587,6 +612,7 @@ define float @test_fsub(float %arg1, float %arg2) {
|
|||
; CHECK-LABEL: name: test_fmul
|
||||
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
|
||||
; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
|
||||
; CHECK: bb.1:
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FMUL [[ARG1]], [[ARG2]]
|
||||
; CHECK-NEXT: %s0 = COPY [[RES]]
|
||||
; CHECK-NEXT: RET_ReallyLR implicit %s0
|
||||
|
|
@ -598,6 +624,7 @@ define float @test_fmul(float %arg1, float %arg2) {
|
|||
; CHECK-LABEL: name: test_fdiv
|
||||
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
|
||||
; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
|
||||
; CHECK: bb.1:
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FDIV [[ARG1]], [[ARG2]]
|
||||
; CHECK-NEXT: %s0 = COPY [[RES]]
|
||||
; CHECK-NEXT: RET_ReallyLR implicit %s0
|
||||
|
|
@ -609,6 +636,7 @@ define float @test_fdiv(float %arg1, float %arg2) {
|
|||
; CHECK-LABEL: name: test_frem
|
||||
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
|
||||
; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
|
||||
; CHECK: bb.1:
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FREM [[ARG1]], [[ARG2]]
|
||||
; CHECK-NEXT: %s0 = COPY [[RES]]
|
||||
; CHECK-NEXT: RET_ReallyLR implicit %s0
|
||||
|
|
@ -929,14 +957,18 @@ define void @test_large_const(i128* %addr) {
|
|||
|
||||
; When there was no formal argument handling (so the first BB was empty) we used
|
||||
; to insert the constants at the end of the block, even if they were encountered
|
||||
; after the block's terminators had been emitted.
|
||||
define i32 @test_const_placement() {
|
||||
; after the block's terminators had been emitted. Also make sure the order is
|
||||
; correct.
|
||||
define i8* @test_const_placement() {
|
||||
; CHECK-LABEL: name: test_const_placement
|
||||
; CHECK: [[VAL:%[0-9]+]](s32) = G_CONSTANT i32 42
|
||||
; CHECK: G_BR
|
||||
|
||||
; CHECK: bb.0:
|
||||
; CHECK: [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
|
||||
; CHECK: bb.1:
|
||||
; CHECK: G_BR
|
||||
; CHECK: bb.2:
|
||||
; CHECK: [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
|
||||
br label %next
|
||||
|
||||
next:
|
||||
ret i32 42
|
||||
ret i8* inttoptr(i32 42 to i8*)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,8 +18,8 @@ define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs)
|
|||
}
|
||||
|
||||
; CHECK-LABEL: name: test_call_stack
|
||||
; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
|
||||
; CHECK: [[C42:%[0-9]+]](s8) = G_CONSTANT i8 42
|
||||
; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
|
||||
; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
|
||||
; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
|
||||
; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
|
||||
|
|
|
|||
|
|
@ -162,9 +162,9 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
|
|||
}
|
||||
|
||||
; CHECK-LABEL: name: test_call_stack
|
||||
; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
|
||||
; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
|
||||
; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42
|
||||
; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
|
||||
; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
|
||||
; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
|
||||
; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
|
||||
; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
|
||||
|
|
|
|||
|
|
@ -9,14 +9,15 @@ declare i32 @llvm.eh.typeid.for(i8*)
|
|||
; CHECK: name: bar
|
||||
; CHECK: body:
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.2{{.*}}%bb.1
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
|
||||
; CHECK: EH_LABEL
|
||||
; CHECK: %w0 = COPY
|
||||
; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
|
||||
; CHECK: {{%[0-9]+}}(s32) = COPY %w0
|
||||
; CHECK: EH_LABEL
|
||||
|
||||
; CHECK: bb.1
|
||||
; CHECK: [[BAD]] (landing-pad):
|
||||
; CHECK: EH_LABEL
|
||||
; CHECK: [[PTR:%[0-9]+]](p0) = COPY %x0
|
||||
; CHECK: [[SEL:%[0-9]+]](p0) = COPY %x1
|
||||
|
|
@ -25,7 +26,7 @@ declare i32 @llvm.eh.typeid.for(i8*)
|
|||
; CHECK: %x0 = COPY [[PTR_RET]]
|
||||
; CHECK: %w1 = COPY [[SEL_RET]]
|
||||
|
||||
; CHECK: bb.2:
|
||||
; CHECK: [[GOOD]]:
|
||||
; CHECK: [[SEL:%[0-9]+]](s32) = G_CONSTANT i32 1
|
||||
; CHECK: {{%[0-9]+}}(s128) = G_INSERT {{%[0-9]+}}(s128), [[SEL]](s32), 64
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@ define void @test_void_return() {
|
|||
; CHECK-NEXT: hasMustTailInVarArgFunc: false
|
||||
; CHECK-NEXT: body:
|
||||
; CHECK-NEXT: bb.0:
|
||||
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
||||
; CHECK: bb.1:
|
||||
; CHECK-NEXT: RET 0
|
||||
entry:
|
||||
ret void
|
||||
|
|
|
|||
Loading…
Reference in New Issue