[X86] Update LLC tests for slow division bypassing (NFC)
Run update_llc_test_checks.py on
CodeGen/X86/atom-bypass-slow-division.ll
CodeGen/X86/atom-bypass-slow-division-64.ll
CodeGen/X86/slow-div.ll
Differential Revision: https://reviews.llvm.org/D28469
llvm-svn: 291799
This commit is contained in:
Nikolai Bozhenov
parent
9d1ed00a00
commit
05b4095990
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@ -1,49 +1,74 @@
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; RUN: llc < %s -mcpu=atom -march=x86-64 | FileCheck %s
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target triple = "x86_64-unknown-linux-gnu"
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mcpu=atom -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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; Additional tests for 64-bit divide bypass
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define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: Test_get_quotient:
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; CHECK: movq %rdi, %rax
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; CHECK: orq %rsi, %rax
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; CHECK-NEXT: testq $-65536, %rax
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; CHECK-NEXT: je
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; CHECK: idivq
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; CHECK: ret
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; CHECK: divw
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; CHECK: ret
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; CHECK: # BB#0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: orq %rsi, %rax
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; CHECK-NEXT: testq $-65536, %rax # imm = 0xFFFF0000
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; CHECK-NEXT: je .LBB0_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: cqto
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; CHECK-NEXT: idivq %rsi
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: divw %si
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: retq
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%result = sdiv i64 %a, %b
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ret i64 %result
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}
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define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: Test_get_remainder:
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; CHECK: movq %rdi, %rax
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; CHECK: orq %rsi, %rax
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; CHECK-NEXT: testq $-65536, %rax
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; CHECK-NEXT: je
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; CHECK: idivq
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; CHECK: ret
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; CHECK: divw
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; CHECK: ret
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; CHECK: # BB#0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: orq %rsi, %rax
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; CHECK-NEXT: testq $-65536, %rax # imm = 0xFFFF0000
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; CHECK-NEXT: je .LBB1_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: cqto
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; CHECK-NEXT: idivq %rsi
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; CHECK-NEXT: movq %rdx, %rax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB1_1:
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: divw %si
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; CHECK-NEXT: movzwl %dx, %eax
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; CHECK-NEXT: retq
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%result = srem i64 %a, %b
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ret i64 %result
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}
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define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: Test_get_quotient_and_remainder:
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; CHECK: movq %rdi, %rax
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; CHECK: orq %rsi, %rax
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; CHECK-NEXT: testq $-65536, %rax
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; CHECK-NEXT: je
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; CHECK: idivq
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; CHECK: divw
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; CHECK: addq
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; CHECK: ret
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; CHECK-NOT: idivq
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; CHECK-NOT: divw
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; CHECK: # BB#0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: orq %rsi, %rax
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; CHECK-NEXT: testq $-65536, %rax # imm = 0xFFFF0000
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; CHECK-NEXT: je .LBB2_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: cqto
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; CHECK-NEXT: idivq %rsi
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; CHECK-NEXT: addq %rdx, %rax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB2_1:
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: divw %si
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: movzwl %dx, %edx
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; CHECK-NEXT: addq %rdx, %rax
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; CHECK-NEXT: retq
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%resultdiv = sdiv i64 %a, %b
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%resultrem = srem i64 %a, %b
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%result = add i64 %resultdiv, %resultrem
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@ -1,42 +1,75 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
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define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: Test_get_quotient:
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; CHECK: orl %ecx, %edx
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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; CHECK-NEXT: je
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; CHECK: idivl
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; CHECK: ret
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; CHECK: divb
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; CHECK: ret
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; CHECK-NEXT: je .LBB0_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %ecx
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
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; CHECK-NEXT: divb %cl
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: retl
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%result = sdiv i32 %a, %b
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ret i32 %result
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}
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define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: Test_get_remainder:
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; CHECK: orl %ecx, %edx
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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; CHECK-NEXT: je
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; CHECK: idivl
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; CHECK: ret
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; CHECK: divb
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; CHECK: ret
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; CHECK-NEXT: je .LBB1_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %ecx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB1_1:
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
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; CHECK-NEXT: divb %cl
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; CHECK-NEXT: movzbl %ah, %eax # NOREX
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; CHECK-NEXT: retl
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%result = srem i32 %a, %b
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ret i32 %result
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}
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define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: Test_get_quotient_and_remainder:
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; CHECK: orl %ecx, %edx
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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; CHECK-NEXT: je
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; CHECK: idivl
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; CHECK: divb
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; CHECK: addl
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; CHECK: ret
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; CHECK-NOT: idivl
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; CHECK-NOT: divb
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; CHECK-NEXT: je .LBB2_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %ecx
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; CHECK-NEXT: addl %edx, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB2_1:
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
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; CHECK-NEXT: divb %cl
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; CHECK-NEXT: movzbl %ah, %edx # NOREX
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: addl %edx, %eax
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; CHECK-NEXT: retl
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%resultdiv = sdiv i32 %a, %b
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%resultrem = srem i32 %a, %b
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%result = add i32 %resultdiv, %resultrem
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@ -45,12 +78,48 @@ define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
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define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: Test_use_div_and_idiv:
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; CHECK: idivl
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; CHECK: divb
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; CHECK: divl
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; CHECK: divb
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; CHECK: addl
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; CHECK: ret
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; CHECK: # BB#0:
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; CHECK-NEXT: pushl %ebx
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; CHECK-NEXT: movl %ecx, %edi
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; CHECK-NEXT: orl %ebx, %edi
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; CHECK-NEXT: testl $-256, %edi
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; CHECK-NEXT: je .LBB3_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %ebx
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; CHECK-NEXT: movl %eax, %esi
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; CHECK-NEXT: testl $-256, %edi
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; CHECK-NEXT: jne .LBB3_5
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; CHECK-NEXT: jmp .LBB3_4
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; CHECK-NEXT: .LBB3_1:
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
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; CHECK-NEXT: divb %bl
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; CHECK-NEXT: movzbl %al, %esi
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; CHECK-NEXT: testl $-256, %edi
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; CHECK-NEXT: je .LBB3_4
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; CHECK-NEXT: .LBB3_5:
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: divl %ebx
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; CHECK-NEXT: jmp .LBB3_6
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; CHECK-NEXT: .LBB3_4:
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
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; CHECK-NEXT: divb %bl
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: .LBB3_6:
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; CHECK-NEXT: addl %eax, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: popl %ebx
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; CHECK-NEXT: retl
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%resultidiv = sdiv i32 %a, %b
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%resultdiv = udiv i32 %a, %b
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%result = add i32 %resultidiv, %resultdiv
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@ -59,34 +128,72 @@ define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
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define i32 @Test_use_div_imm_imm() nounwind {
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; CHECK-LABEL: Test_use_div_imm_imm:
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; CHECK: movl $64
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $64, %eax
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: retl
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%resultdiv = sdiv i32 256, 4
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ret i32 %resultdiv
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}
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define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
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; CHECK-LABEL: Test_use_div_reg_imm:
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; CHECK-NOT: test
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; CHECK-NOT: idiv
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; CHECK-NOT: divb
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $1041204193, %eax # imm = 0x3E0F83E1
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; CHECK-NEXT: imull {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: leal (%edx,%eax), %eax
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; CHECK-NEXT: retl
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%resultdiv = sdiv i32 %a, 33
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ret i32 %resultdiv
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}
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define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
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; CHECK-LABEL: Test_use_rem_reg_imm:
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; CHECK-NOT: test
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; CHECK-NOT: idiv
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; CHECK-NOT: divb
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: imull %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: addl %eax, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shll $5, %eax
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; CHECK-NEXT: addl %edx, %eax
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; CHECK-NEXT: subl %eax, %ecx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: retl
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%resultrem = srem i32 %a, 33
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ret i32 %resultrem
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}
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define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
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; CHECK-LABEL: Test_use_divrem_reg_imm:
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; CHECK-NOT: test
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; CHECK-NOT: idiv
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; CHECK-NOT: divb
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: imull %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: addl %eax, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shll $5, %eax
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; CHECK-NEXT: addl %edx, %eax
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; CHECK-NEXT: subl %eax, %ecx
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; CHECK-NEXT: addl %edx, %ecx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: retl
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%resultdiv = sdiv i32 %a, 33
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%resultrem = srem i32 %a, 33
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%result = add i32 %resultdiv, %resultrem
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@ -95,18 +202,44 @@ define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
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define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
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; CHECK-LABEL: Test_use_div_imm_reg:
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; CHECK: test
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; CHECK: idiv
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; CHECK: divb
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: testl $-256, %ecx
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; CHECK-NEXT: je .LBB8_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: movl $4, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: idivl %ecx
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB8_1:
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; CHECK-NEXT: movb $4, %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
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; CHECK-NEXT: divb %cl
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: retl
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%resultdiv = sdiv i32 4, %a
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ret i32 %resultdiv
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}
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define i32 @Test_use_rem_imm_reg(i32 %a) nounwind {
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; CHECK-LABEL: Test_use_rem_imm_reg:
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; CHECK: test
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; CHECK: idiv
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; CHECK: divb
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: testl $-256, %ecx
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; CHECK-NEXT: je .LBB9_1
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; CHECK-NEXT: # BB#2:
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; CHECK-NEXT: movl $4, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: idivl %ecx
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB9_1:
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; CHECK-NEXT: movb $4, %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
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; CHECK-NEXT: divb %cl
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: retl
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%resultdiv = sdiv i32 4, %a
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ret i32 %resultdiv
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}
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