[Hexagon] Change the vector scaling for vector offsets
Keep full offset value on MI-level instructions, but have it scaled down in the MC-level instructions. llvm-svn: 299664
This commit is contained in:
Krzysztof Parzyszek
parent
9d4d91ca6a
commit
058abf1a4a
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@ -320,10 +320,6 @@ public:
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bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
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bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
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bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
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bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }
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bool iss4_7Imm() const { return CheckImmRange(4, 0, true, false, false); }
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bool iss3_7Imm() const { return CheckImmRange(3, 0, true, false, false); }
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bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }
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bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); }
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bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); }
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@ -406,20 +402,6 @@ public:
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addImmOperands(Inst, N);
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}
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void adds4_6ImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCConstantExpr *CE =
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dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
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Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
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}
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void adds3_6ImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCConstantExpr *CE =
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dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
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Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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@ -148,9 +148,7 @@ static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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@ -631,18 +629,6 @@ static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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signedDecoder<10>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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signedDecoder<19>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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HexagonDisassembler const &Disassembler = disassembler(Decoder);
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@ -261,10 +261,34 @@ static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI,
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return Sym;
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}
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static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
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unsigned VectorSize, MCContext &Ctx) {
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MCInst T;
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T.setOpcode(Inst.getOpcode());
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for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {
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if (i != OpNo) {
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T.addOperand(Inst.getOperand(i));
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continue;
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}
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MCOperand &ImmOp = Inst.getOperand(i);
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const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
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int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();
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auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx);
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auto *NewHE = HexagonMCExpr::create(NewCE, Ctx);
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T.addOperand(MCOperand::createExpr(NewHE));
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}
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return T;
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}
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void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
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const MachineInstr &MI) {
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MCInst &MappedInst = static_cast <MCInst &>(Inst);
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const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
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const MachineFunction &MF = *MI.getParent()->getParent();
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const auto &HST = MF.getSubtarget<HexagonSubtarget>();
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unsigned VectorSize = HST.useHVXSglOps()
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? Hexagon::VectorRegsRegClass.getSize()
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: Hexagon::VectorRegs128BRegClass.getSize();
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switch (Inst.getOpcode()) {
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default: return;
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@ -597,6 +621,181 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
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return;
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}
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case Hexagon::V6_vL32Ub_pi:
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case Hexagon::V6_vL32b_cur_pi:
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case Hexagon::V6_vL32b_nt_cur_pi:
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case Hexagon::V6_vL32b_pi:
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case Hexagon::V6_vL32b_nt_pi:
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case Hexagon::V6_vL32b_nt_tmp_pi:
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case Hexagon::V6_vL32b_tmp_pi:
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case Hexagon::V6_vL32Ub_pi_128B:
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case Hexagon::V6_vL32b_cur_pi_128B:
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case Hexagon::V6_vL32b_nt_cur_pi_128B:
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case Hexagon::V6_vL32b_pi_128B:
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case Hexagon::V6_vL32b_nt_pi_128B:
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case Hexagon::V6_vL32b_nt_tmp_pi_128B:
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case Hexagon::V6_vL32b_tmp_pi_128B:
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MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
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return;
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case Hexagon::V6_vL32Ub_ai:
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case Hexagon::V6_vL32b_ai:
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case Hexagon::V6_vL32b_cur_ai:
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case Hexagon::V6_vL32b_nt_ai:
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case Hexagon::V6_vL32b_nt_cur_ai:
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case Hexagon::V6_vL32b_nt_tmp_ai:
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case Hexagon::V6_vL32b_tmp_ai:
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case Hexagon::V6_vL32Ub_ai_128B:
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case Hexagon::V6_vL32b_ai_128B:
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case Hexagon::V6_vL32b_cur_ai_128B:
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case Hexagon::V6_vL32b_nt_ai_128B:
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case Hexagon::V6_vL32b_nt_cur_ai_128B:
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case Hexagon::V6_vL32b_nt_tmp_ai_128B:
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case Hexagon::V6_vL32b_tmp_ai_128B:
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MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
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return;
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case Hexagon::V6_vS32Ub_pi:
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case Hexagon::V6_vS32b_new_pi:
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case Hexagon::V6_vS32b_nt_new_pi:
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case Hexagon::V6_vS32b_nt_pi:
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case Hexagon::V6_vS32b_pi:
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case Hexagon::V6_vS32Ub_pi_128B:
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case Hexagon::V6_vS32b_new_pi_128B:
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case Hexagon::V6_vS32b_nt_new_pi_128B:
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case Hexagon::V6_vS32b_nt_pi_128B:
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case Hexagon::V6_vS32b_pi_128B:
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MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
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return;
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case Hexagon::V6_vS32Ub_ai:
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case Hexagon::V6_vS32b_ai:
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case Hexagon::V6_vS32b_new_ai:
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case Hexagon::V6_vS32b_nt_ai:
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case Hexagon::V6_vS32b_nt_new_ai:
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case Hexagon::V6_vS32Ub_ai_128B:
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case Hexagon::V6_vS32b_ai_128B:
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case Hexagon::V6_vS32b_new_ai_128B:
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case Hexagon::V6_vS32b_nt_ai_128B:
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case Hexagon::V6_vS32b_nt_new_ai_128B:
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MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
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return;
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case Hexagon::V6_vL32b_cur_npred_pi:
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case Hexagon::V6_vL32b_cur_pred_pi:
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case Hexagon::V6_vL32b_npred_pi:
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case Hexagon::V6_vL32b_nt_cur_npred_pi:
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case Hexagon::V6_vL32b_nt_cur_pred_pi:
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case Hexagon::V6_vL32b_nt_npred_pi:
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case Hexagon::V6_vL32b_nt_pred_pi:
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case Hexagon::V6_vL32b_nt_tmp_npred_pi:
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case Hexagon::V6_vL32b_nt_tmp_pred_pi:
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case Hexagon::V6_vL32b_pred_pi:
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case Hexagon::V6_vL32b_tmp_npred_pi:
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case Hexagon::V6_vL32b_tmp_pred_pi:
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case Hexagon::V6_vL32b_cur_npred_pi_128B:
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case Hexagon::V6_vL32b_cur_pred_pi_128B:
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case Hexagon::V6_vL32b_npred_pi_128B:
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case Hexagon::V6_vL32b_nt_cur_npred_pi_128B:
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case Hexagon::V6_vL32b_nt_cur_pred_pi_128B:
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case Hexagon::V6_vL32b_nt_npred_pi_128B:
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case Hexagon::V6_vL32b_nt_pred_pi_128B:
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case Hexagon::V6_vL32b_nt_tmp_npred_pi_128B:
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case Hexagon::V6_vL32b_nt_tmp_pred_pi_128B:
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case Hexagon::V6_vL32b_pred_pi_128B:
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case Hexagon::V6_vL32b_tmp_npred_pi_128B:
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case Hexagon::V6_vL32b_tmp_pred_pi_128B:
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MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
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return;
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case Hexagon::V6_vL32b_cur_npred_ai:
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case Hexagon::V6_vL32b_cur_pred_ai:
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case Hexagon::V6_vL32b_npred_ai:
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case Hexagon::V6_vL32b_nt_cur_npred_ai:
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case Hexagon::V6_vL32b_nt_cur_pred_ai:
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case Hexagon::V6_vL32b_nt_npred_ai:
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case Hexagon::V6_vL32b_nt_pred_ai:
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case Hexagon::V6_vL32b_nt_tmp_npred_ai:
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case Hexagon::V6_vL32b_nt_tmp_pred_ai:
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case Hexagon::V6_vL32b_pred_ai:
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case Hexagon::V6_vL32b_tmp_npred_ai:
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case Hexagon::V6_vL32b_tmp_pred_ai:
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case Hexagon::V6_vL32b_cur_npred_ai_128B:
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case Hexagon::V6_vL32b_cur_pred_ai_128B:
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case Hexagon::V6_vL32b_npred_ai_128B:
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case Hexagon::V6_vL32b_nt_cur_npred_ai_128B:
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case Hexagon::V6_vL32b_nt_cur_pred_ai_128B:
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case Hexagon::V6_vL32b_nt_npred_ai_128B:
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case Hexagon::V6_vL32b_nt_pred_ai_128B:
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case Hexagon::V6_vL32b_nt_tmp_npred_ai_128B:
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case Hexagon::V6_vL32b_nt_tmp_pred_ai_128B:
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case Hexagon::V6_vL32b_pred_ai_128B:
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case Hexagon::V6_vL32b_tmp_npred_ai_128B:
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case Hexagon::V6_vL32b_tmp_pred_ai_128B:
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MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
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return;
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case Hexagon::V6_vS32Ub_npred_pi:
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case Hexagon::V6_vS32Ub_pred_pi:
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case Hexagon::V6_vS32b_new_npred_pi:
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case Hexagon::V6_vS32b_new_pred_pi:
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case Hexagon::V6_vS32b_npred_pi:
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case Hexagon::V6_vS32b_nqpred_pi:
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case Hexagon::V6_vS32b_nt_new_npred_pi:
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case Hexagon::V6_vS32b_nt_new_pred_pi:
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case Hexagon::V6_vS32b_nt_npred_pi:
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case Hexagon::V6_vS32b_nt_nqpred_pi:
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case Hexagon::V6_vS32b_nt_pred_pi:
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case Hexagon::V6_vS32b_nt_qpred_pi:
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case Hexagon::V6_vS32b_pred_pi:
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case Hexagon::V6_vS32b_qpred_pi:
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case Hexagon::V6_vS32Ub_npred_pi_128B:
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case Hexagon::V6_vS32Ub_pred_pi_128B:
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case Hexagon::V6_vS32b_new_npred_pi_128B:
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case Hexagon::V6_vS32b_new_pred_pi_128B:
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case Hexagon::V6_vS32b_npred_pi_128B:
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case Hexagon::V6_vS32b_nqpred_pi_128B:
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case Hexagon::V6_vS32b_nt_new_npred_pi_128B:
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case Hexagon::V6_vS32b_nt_new_pred_pi_128B:
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case Hexagon::V6_vS32b_nt_npred_pi_128B:
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case Hexagon::V6_vS32b_nt_nqpred_pi_128B:
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case Hexagon::V6_vS32b_nt_pred_pi_128B:
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case Hexagon::V6_vS32b_nt_qpred_pi_128B:
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case Hexagon::V6_vS32b_pred_pi_128B:
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case Hexagon::V6_vS32b_qpred_pi_128B:
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MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
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return;
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case Hexagon::V6_vS32Ub_npred_ai:
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case Hexagon::V6_vS32Ub_pred_ai:
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case Hexagon::V6_vS32b_new_npred_ai:
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case Hexagon::V6_vS32b_new_pred_ai:
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case Hexagon::V6_vS32b_npred_ai:
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case Hexagon::V6_vS32b_nqpred_ai:
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case Hexagon::V6_vS32b_nt_new_npred_ai:
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case Hexagon::V6_vS32b_nt_new_pred_ai:
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case Hexagon::V6_vS32b_nt_npred_ai:
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case Hexagon::V6_vS32b_nt_nqpred_ai:
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case Hexagon::V6_vS32b_nt_pred_ai:
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case Hexagon::V6_vS32b_nt_qpred_ai:
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case Hexagon::V6_vS32b_pred_ai:
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case Hexagon::V6_vS32b_qpred_ai:
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case Hexagon::V6_vS32Ub_npred_ai_128B:
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case Hexagon::V6_vS32Ub_pred_ai_128B:
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case Hexagon::V6_vS32b_new_npred_ai_128B:
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case Hexagon::V6_vS32b_new_pred_ai_128B:
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case Hexagon::V6_vS32b_npred_ai_128B:
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case Hexagon::V6_vS32b_nqpred_ai_128B:
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case Hexagon::V6_vS32b_nt_new_npred_ai_128B:
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case Hexagon::V6_vS32b_nt_new_pred_ai_128B:
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case Hexagon::V6_vS32b_nt_npred_ai_128B:
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case Hexagon::V6_vS32b_nt_nqpred_ai_128B:
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case Hexagon::V6_vS32b_nt_pred_ai_128B:
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case Hexagon::V6_vS32b_nt_qpred_ai_128B:
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case Hexagon::V6_vS32b_pred_ai_128B:
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case Hexagon::V6_vS32b_qpred_ai_128B:
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MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
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return;
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}
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}
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@ -32,6 +32,11 @@ static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
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signedDecoder<12>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<3>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<13>(MI, tmp, Decoder);
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@ -28,8 +28,8 @@ class Enc_16626097 : OpcodeHexagon {
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let Inst{4-0} = Vw32{4-0};
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}
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class Enc_13397056 : OpcodeHexagon {
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bits <10> Ii;
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let Inst{10-8} = Ii{9-7};
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bits <3> Ii;
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let Inst{10-8} = Ii{2-0};
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bits <2> Qv4;
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let Inst{12-11} = Qv4{1-0};
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bits <5> Vs32;
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@ -49,15 +49,6 @@ class Enc_7315939 : OpcodeHexagon {
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let Inst{13-13} = n1{1-1};
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let Inst{8-8} = n1{0-0};
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}
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class Enc_605928 : OpcodeHexagon {
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bits <10> Ii;
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let Inst{13-13} = Ii{9-9};
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let Inst{10-8} = Ii{8-6};
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bits <5> Rt32;
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let Inst{20-16} = Rt32{4-0};
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bits <5> Zdd8;
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let Inst{4-0} = Zdd8{4-0};
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}
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class Enc_15275738 : OpcodeHexagon {
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bits <12> Ii;
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let Inst{26-25} = Ii{11-10};
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@ -231,15 +222,6 @@ class Enc_1971351 : OpcodeHexagon {
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bits <5> Rx32;
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let Inst{20-16} = Rx32{4-0};
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}
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class Enc_12373826 : OpcodeHexagon {
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bits <11> Ii;
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let Inst{13-13} = Ii{10-10};
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let Inst{10-8} = Ii{9-7};
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bits <5> Rt32;
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let Inst{20-16} = Rt32{4-0};
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bits <5> Zdd8;
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let Inst{4-0} = Zdd8{4-0};
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}
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class Enc_13715847 : OpcodeHexagon {
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bits <6> Ii;
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let Inst{17-16} = Ii{5-4};
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|
|
@ -315,23 +297,6 @@ class Enc_10492541 : OpcodeHexagon {
|
|||
}
|
||||
class Enc_0 : OpcodeHexagon {
|
||||
}
|
||||
class Enc_8868098 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{21-21} = Ii{9-9};
|
||||
let Inst{13-8} = Ii{8-3};
|
||||
let Inst{2-0} = Ii{2-0};
|
||||
bits <5> Vss32;
|
||||
let Inst{7-3} = Vss32{4-0};
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_10380392 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{13-13} = Ii{10-10};
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
}
|
||||
class Enc_15733946 : OpcodeHexagon {
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
|
|
@ -343,9 +308,9 @@ class Enc_15733946 : OpcodeHexagon {
|
|||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_738356 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{13-13} = Ii{10-10};
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Rt32;
|
||||
|
|
@ -353,14 +318,6 @@ class Enc_738356 : OpcodeHexagon {
|
|||
bits <5> Vd32;
|
||||
let Inst{4-0} = Vd32{4-0};
|
||||
}
|
||||
class Enc_15578334 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <5> Zdd8;
|
||||
let Inst{4-0} = Zdd8{4-0};
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_14400220 : OpcodeHexagon {
|
||||
bits <5> Ii;
|
||||
let Inst{9-5} = Ii{4-0};
|
||||
|
|
@ -425,9 +382,9 @@ class Enc_14620934 : OpcodeHexagon {
|
|||
let Inst{12-8} = Rt32{4-0};
|
||||
}
|
||||
class Enc_10075393 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{13-13} = Ii{9-9};
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Rt32;
|
||||
|
|
@ -927,8 +884,8 @@ class Enc_9305257 : OpcodeHexagon {
|
|||
let Inst{4-0} = Vd32{4-0};
|
||||
}
|
||||
class Enc_3735566 : OpcodeHexagon {
|
||||
bits <9> Ii;
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <3> Os8;
|
||||
|
|
@ -1033,9 +990,9 @@ class Enc_10263630 : OpcodeHexagon {
|
|||
let Inst{7-3} = Vx32{4-0};
|
||||
}
|
||||
class Enc_13937564 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{13-13} = Ii{10-10};
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Rt32;
|
||||
|
|
@ -1220,8 +1177,8 @@ class Enc_7912540 : OpcodeHexagon {
|
|||
let Inst{4-0} = Rxx32{4-0};
|
||||
}
|
||||
class Enc_15560488 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Vd32;
|
||||
|
|
@ -1361,9 +1318,9 @@ class Enc_5636753 : OpcodeHexagon {
|
|||
let Inst{20-16} = Vu32{4-0};
|
||||
}
|
||||
class Enc_5757366 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{13-13} = Ii{10-10};
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
bits <5> Vs32;
|
||||
|
|
@ -1421,9 +1378,9 @@ class Enc_9773189 : OpcodeHexagon {
|
|||
let Inst{12-8} = Rxx32{4-0};
|
||||
}
|
||||
class Enc_2152247 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{13-13} = Ii{10-10};
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
bits <3> Os8;
|
||||
|
|
@ -1441,9 +1398,9 @@ class Enc_12848507 : OpcodeHexagon {
|
|||
let Inst{12-8} = Rtt32{4-0};
|
||||
}
|
||||
class Enc_16279406 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{13-13} = Ii{9-9};
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Qv4;
|
||||
let Inst{12-11} = Qv4{1-0};
|
||||
bits <5> Rt32;
|
||||
|
|
@ -1499,8 +1456,8 @@ class Enc_4109168 : OpcodeHexagon {
|
|||
let Inst{23-22} = Qv4{1-0};
|
||||
}
|
||||
class Enc_14560494 : OpcodeHexagon {
|
||||
bits <9> Ii;
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Vd32;
|
||||
|
|
@ -1532,8 +1489,8 @@ class Enc_11498120 : OpcodeHexagon {
|
|||
let Inst{1-0} = Qd4{1-0};
|
||||
}
|
||||
class Enc_15459921 : OpcodeHexagon {
|
||||
bits <9> Ii;
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Vs32;
|
||||
|
|
@ -1777,9 +1734,9 @@ class Enc_48594 : OpcodeHexagon {
|
|||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_6608821 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{13-13} = Ii{9-9};
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
bits <3> Os8;
|
||||
|
|
@ -2003,19 +1960,13 @@ class Enc_16319737 : OpcodeHexagon {
|
|||
let Inst{12-8} = Rtt32{4-0};
|
||||
}
|
||||
class Enc_2296022 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Vs32;
|
||||
let Inst{4-0} = Vs32{4-0};
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_14546668 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_9664427 : OpcodeHexagon {
|
||||
bits <5> Vuu32;
|
||||
let Inst{20-16} = Vuu32{4-0};
|
||||
|
|
@ -2249,9 +2200,9 @@ class Enc_13174858 : OpcodeHexagon {
|
|||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_8437395 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{13-13} = Ii{10-10};
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
bits <5> Vd32;
|
||||
|
|
@ -2301,8 +2252,8 @@ class Enc_64199 : OpcodeHexagon {
|
|||
let Inst{3-0} = Rd16{3-0};
|
||||
}
|
||||
class Enc_11039423 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Vd32;
|
||||
let Inst{4-0} = Vd32{4-0};
|
||||
bits <5> Rx32;
|
||||
|
|
@ -2336,9 +2287,9 @@ class Enc_13204995 : OpcodeHexagon {
|
|||
let Inst{3-0} = Rt16{3-0};
|
||||
}
|
||||
class Enc_13338314 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{13-13} = Ii{9-9};
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Rt32;
|
||||
|
|
@ -2370,8 +2321,8 @@ class Enc_15380240 : OpcodeHexagon {
|
|||
let Inst{12-8} = Vy32{4-0};
|
||||
}
|
||||
class Enc_3296020 : OpcodeHexagon {
|
||||
bits <9> Ii;
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Vs32;
|
||||
let Inst{4-0} = Vs32{4-0};
|
||||
bits <5> Rx32;
|
||||
|
|
@ -2389,17 +2340,17 @@ class Enc_2428539 : OpcodeHexagon {
|
|||
let Inst{8-8} = n1{0-0};
|
||||
}
|
||||
class Enc_10039393 : OpcodeHexagon {
|
||||
bits <9> Ii;
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Vd32;
|
||||
let Inst{4-0} = Vd32{4-0};
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_9372046 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{13-13} = Ii{9-9};
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Rt32;
|
||||
|
|
@ -2425,16 +2376,6 @@ class Enc_16145290 : OpcodeHexagon {
|
|||
bits <5> Vdd32;
|
||||
let Inst{4-0} = Vdd32{4-0};
|
||||
}
|
||||
class Enc_5555790 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{21-21} = Ii{9-9};
|
||||
let Inst{13-8} = Ii{8-3};
|
||||
let Inst{2-0} = Ii{2-0};
|
||||
bits <5> Vs32;
|
||||
let Inst{7-3} = Vs32{4-0};
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_13783220 : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
|
|
@ -2598,9 +2539,9 @@ class Enc_11081334 : OpcodeHexagon {
|
|||
let Inst{7-3} = Vss32{4-0};
|
||||
}
|
||||
class Enc_9470751 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{13-13} = Ii{10-10};
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Rt32;
|
||||
|
|
@ -3126,9 +3067,9 @@ class Enc_5023792 : OpcodeHexagon {
|
|||
let Inst{4-0} = Vdd32{4-0};
|
||||
}
|
||||
class Enc_1244745 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{13-13} = Ii{9-9};
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
bits <5> Vd32;
|
||||
|
|
@ -3162,9 +3103,9 @@ class Enc_1774350 : OpcodeHexagon {
|
|||
let Inst{10-8} = Nt8{2-0};
|
||||
}
|
||||
class Enc_2703240 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{13-13} = Ii{10-10};
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Qv4;
|
||||
let Inst{12-11} = Qv4{1-0};
|
||||
bits <5> Rt32;
|
||||
|
|
@ -3187,8 +3128,8 @@ class Enc_9789480 : OpcodeHexagon {
|
|||
let Inst{7-3} = Vdd32{4-0};
|
||||
}
|
||||
class Enc_12244921 : OpcodeHexagon {
|
||||
bits <9> Ii;
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <6> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <3> Os8;
|
||||
let Inst{2-0} = Os8{2-0};
|
||||
bits <5> Rx32;
|
||||
|
|
@ -3508,13 +3449,6 @@ class Enc_11065510 : OpcodeHexagon {
|
|||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_8829170 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{13-13} = Ii{9-9};
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
}
|
||||
class Enc_6673186 : OpcodeHexagon {
|
||||
bits <13> Ii;
|
||||
let Inst{26-25} = Ii{12-11};
|
||||
|
|
@ -3669,9 +3603,9 @@ class Enc_15946706 : OpcodeHexagon {
|
|||
let Inst{2-0} = Rdd8{2-0};
|
||||
}
|
||||
class Enc_6923828 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{13-13} = Ii{9-9};
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
bits <5> Vs32;
|
||||
|
|
@ -3898,8 +3832,8 @@ class Enc_7884306 : OpcodeHexagon {
|
|||
let Inst{8-4} = Ii{7-3};
|
||||
}
|
||||
class Enc_11244923 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <3> Os8;
|
||||
let Inst{2-0} = Os8{2-0};
|
||||
bits <5> Rx32;
|
||||
|
|
@ -3946,8 +3880,8 @@ class Enc_5915771 : OpcodeHexagon {
|
|||
let Inst{8-8} = n1{0-0};
|
||||
}
|
||||
class Enc_14459927 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Vs32;
|
||||
|
|
@ -4146,8 +4080,8 @@ class Enc_11940513 : OpcodeHexagon {
|
|||
let Inst{4-0} = Rt32{4-0};
|
||||
}
|
||||
class Enc_2735552 : OpcodeHexagon {
|
||||
bits <10> Ii;
|
||||
let Inst{10-8} = Ii{9-7};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <3> Os8;
|
||||
|
|
@ -4227,8 +4161,8 @@ class Enc_14631806 : OpcodeHexagon {
|
|||
let Inst{4-0} = Vdd32{4-0};
|
||||
}
|
||||
class Enc_12397062 : OpcodeHexagon {
|
||||
bits <9> Ii;
|
||||
let Inst{10-8} = Ii{8-6};
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Qv4;
|
||||
let Inst{12-11} = Qv4{1-0};
|
||||
bits <5> Vs32;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -7,6 +7,9 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; }
|
||||
def s3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
|
||||
def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; }
|
||||
def s4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
|
||||
|
|
@ -70,9 +73,6 @@ def s6_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<6, 0>(N->getSExtValu
|
|||
def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
def u5_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>;
|
||||
def s4_7ImmOperand : AsmOperandClass { let Name = "s4_7Imm"; }
|
||||
def s4_7Imm : Operand<i32> { let ParserMatchClass = s4_7ImmOperand; let DecoderMethod = "s4_7ImmDecoder"; let PrintMethod = "prints4_7ImmOperand"; }
|
||||
def s4_7ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 7>(N->getSExtValue());}]>;
|
||||
def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; }
|
||||
def s32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
|
||||
|
|
@ -82,9 +82,6 @@ def s6_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<6, 3>(N->getSExtValu
|
|||
def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
def u10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
|
||||
def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }
|
||||
def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand; let DecoderMethod = "s3_6ImmDecoder"; let PrintMethod = "prints3_6ImmOperand"; }
|
||||
def s3_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 6>(N->getSExtValue());}]>;
|
||||
def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
def u31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>;
|
||||
|
|
@ -127,15 +124,9 @@ def b30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtVa
|
|||
def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
def u8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>;
|
||||
def s3_7ImmOperand : AsmOperandClass { let Name = "s3_7Imm"; }
|
||||
def s3_7Imm : Operand<i32> { let ParserMatchClass = s3_7ImmOperand; let DecoderMethod = "s3_7ImmDecoder"; let PrintMethod = "prints3_7ImmOperand"; }
|
||||
def s3_7ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 7>(N->getSExtValue());}]>;
|
||||
def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
def u30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>;
|
||||
def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }
|
||||
def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand; let DecoderMethod = "s4_6ImmDecoder"; let PrintMethod = "prints4_6ImmOperand"; }
|
||||
def s4_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 6>(N->getSExtValue());}]>;
|
||||
def s10_0ImmOperand : AsmOperandClass { let Name = "s10_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s10_0Imm : Operand<i32> { let ParserMatchClass = s10_0ImmOperand; let DecoderMethod = "s10_0ImmDecoder"; }
|
||||
def s10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 0>(N->getSExtValue());}]>;
|
||||
|
|
|
|||
|
|
@ -17,6 +17,16 @@ def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
|
|||
def IsOrAdd: PatFrag<(ops node:$Addr, node:$off),
|
||||
(or node:$Addr, node:$off), [{ return isOrEquivalentToAdd(N); }]>;
|
||||
|
||||
def Iss4_6 : PatLeaf<(i32 imm), [{
|
||||
int32_t V = N->getSExtValue();
|
||||
return isShiftedInt<4,6>(V);
|
||||
}]>;
|
||||
|
||||
def Iss4_7 : PatLeaf<(i32 imm), [{
|
||||
int32_t V = N->getSExtValue();
|
||||
return isShiftedInt<4,7>(V);
|
||||
}]>;
|
||||
|
||||
def IsPow2_32 : PatLeaf<(i32 imm), [{
|
||||
uint32_t V = N->getZExtValue();
|
||||
return isPowerOf2_32(V);
|
||||
|
|
@ -2746,25 +2756,25 @@ multiclass vS32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
|
|||
// Fold Add R+OFF into vector store.
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat<(alignedstore (VTSgl VectorRegs:$src1),
|
||||
(add IntRegs:$src2, s4_6ImmPred:$offset)),
|
||||
(V6_vS32b_ai IntRegs:$src2, s4_6ImmPred:$offset,
|
||||
(add IntRegs:$src2, Iss4_6:$offset)),
|
||||
(V6_vS32b_ai IntRegs:$src2, Iss4_6:$offset,
|
||||
(VTSgl VectorRegs:$src1))>,
|
||||
Requires<[UseHVXSgl]>;
|
||||
def : Pat<(unalignedstore (VTSgl VectorRegs:$src1),
|
||||
(add IntRegs:$src2, s4_6ImmPred:$offset)),
|
||||
(V6_vS32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset,
|
||||
(add IntRegs:$src2, Iss4_6:$offset)),
|
||||
(V6_vS32Ub_ai IntRegs:$src2, Iss4_6:$offset,
|
||||
(VTSgl VectorRegs:$src1))>,
|
||||
Requires<[UseHVXSgl]>;
|
||||
|
||||
// Fold Add R+OFF into vector store 128B.
|
||||
def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1),
|
||||
(add IntRegs:$src2, s4_7ImmPred:$offset)),
|
||||
(V6_vS32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
|
||||
(add IntRegs:$src2, Iss4_7:$offset)),
|
||||
(V6_vS32b_ai_128B IntRegs:$src2, Iss4_7:$offset,
|
||||
(VTDbl VectorRegs128B:$src1))>,
|
||||
Requires<[UseHVXDbl]>;
|
||||
def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1),
|
||||
(add IntRegs:$src2, s4_7ImmPred:$offset)),
|
||||
(V6_vS32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
|
||||
(add IntRegs:$src2, Iss4_7:$offset)),
|
||||
(V6_vS32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset,
|
||||
(VTDbl VectorRegs128B:$src1))>,
|
||||
Requires<[UseHVXDbl]>;
|
||||
}
|
||||
|
|
@ -2795,18 +2805,18 @@ multiclass vL32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
|
|||
|
||||
// Fold Add R+OFF into vector load.
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat<(VTDbl (alignedload (add IntRegs:$src2, s4_7ImmPred:$offset))),
|
||||
(V6_vL32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
|
||||
def : Pat<(VTDbl (alignedload (add IntRegs:$src2, Iss4_7:$offset))),
|
||||
(V6_vL32b_ai_128B IntRegs:$src2, Iss4_7:$offset)>,
|
||||
Requires<[UseHVXDbl]>;
|
||||
def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, s4_7ImmPred:$offset))),
|
||||
(V6_vL32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
|
||||
def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, Iss4_7:$offset))),
|
||||
(V6_vL32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset)>,
|
||||
Requires<[UseHVXDbl]>;
|
||||
|
||||
def : Pat<(VTSgl (alignedload (add IntRegs:$src2, s4_6ImmPred:$offset))),
|
||||
(V6_vL32b_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
|
||||
def : Pat<(VTSgl (alignedload (add IntRegs:$src2, Iss4_6:$offset))),
|
||||
(V6_vL32b_ai IntRegs:$src2, Iss4_6:$offset)>,
|
||||
Requires<[UseHVXSgl]>;
|
||||
def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, s4_6ImmPred:$offset))),
|
||||
(V6_vL32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
|
||||
def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, Iss4_6:$offset))),
|
||||
(V6_vL32Ub_ai IntRegs:$src2, Iss4_6:$offset)>,
|
||||
Requires<[UseHVXSgl]>;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -125,46 +125,6 @@ void HexagonInstPrinter::printNOneImmOperand(MCInst const *MI, unsigned OpNo,
|
|||
O << -1;
|
||||
}
|
||||
|
||||
void HexagonInstPrinter::prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const {
|
||||
int64_t Imm;
|
||||
bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
|
||||
Imm = SignExtend64<9>(Imm);
|
||||
assert(Success); (void)Success;
|
||||
assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
|
||||
O << formatImm(Imm/64);
|
||||
}
|
||||
|
||||
void HexagonInstPrinter::prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const {
|
||||
int64_t Imm;
|
||||
bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
|
||||
Imm = SignExtend64<10>(Imm);
|
||||
assert(Success); (void)Success;
|
||||
assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO.");
|
||||
O << formatImm(Imm/128);
|
||||
}
|
||||
|
||||
void HexagonInstPrinter::prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const {
|
||||
int64_t Imm;
|
||||
bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
|
||||
Imm = SignExtend64<10>(Imm);
|
||||
assert(Success); (void)Success;
|
||||
assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
|
||||
O << formatImm(Imm/64);
|
||||
}
|
||||
|
||||
void HexagonInstPrinter::prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const {
|
||||
int64_t Imm;
|
||||
bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
|
||||
Imm = SignExtend64<11>(Imm);
|
||||
assert(Success); (void)Success;
|
||||
assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO.");
|
||||
O << formatImm(Imm/128);
|
||||
}
|
||||
|
||||
void HexagonInstPrinter::printGlobalOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const {
|
||||
printOperand(MI, OpNo, O);
|
||||
|
|
|
|||
|
|
@ -44,14 +44,6 @@ public:
|
|||
raw_ostream &O) const;
|
||||
void printNOneImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const;
|
||||
void prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const;
|
||||
void prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const;
|
||||
void prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const;
|
||||
void prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const;
|
||||
void printBranchOperand(MCInst const *MI, unsigned OpNo,
|
||||
raw_ostream &O) const;
|
||||
void printCallOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;
|
||||
|
|
|
|||
Loading…
Reference in New Issue