diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp index c9b3dc02597e..0220e7ddacb2 100644 --- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp @@ -988,7 +988,7 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, return; } - // Set bit I(25), because this is not in immediate enconding. + // Set bit I(25), because this is not in immediate encoding. Binary |= 1 << ARMII::I_BitShift; assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); // Set bit[3:0] to the corresponding Rm register diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index c5268d93f9e1..0b9da8a26ef3 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -51,9 +51,9 @@ def vfp_f64imm : Operand, // let canFoldAsLoad = 1, isReMaterializable = 1 in { -def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr), - IIC_fpLoad64, "vldr", ".64\t$dst, $addr", - [(set DPR:$dst, (f64 (load addrmode5:$addr)))]>; +def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), + IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", + [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr), IIC_fpLoad32, "vldr", ".32\t$dst, $addr", @@ -469,13 +469,39 @@ def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0, // FP <-> GPR Copies. Int <-> FP Conversions. // -def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src), - IIC_fpMOVSI, "vmov", "\t$dst, $src", - [(set GPR:$dst, (bitconvert SPR:$src))]>; +def VMOVRS : AVConv2I<0b11100001, 0b1010, + (outs GPR:$Rt), (ins SPR:$Sn), + IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", + [(set GPR:$Rt, (bitconvert SPR:$Sn))]> { + // Instruction operands. + bits<4> Rt; + bits<5> Sn; -def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src), - IIC_fpMOVIS, "vmov", "\t$dst, $src", - [(set SPR:$dst, (bitconvert GPR:$src))]>; + // Encode instruction operands. + let Inst{19-16} = Sn{4-1}; + let Inst{7} = Sn{0}; + let Inst{15-12} = Rt; + + let Inst{6-5} = 0b00; + let Inst{3-0} = 0b0000; +} + +def VMOVSR : AVConv4I<0b11100000, 0b1010, + (outs SPR:$Sn), (ins GPR:$Rt), + IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", + [(set SPR:$Sn, (bitconvert GPR:$Rt))]> { + // Instruction operands. + bits<5> Sn; + bits<4> Rt; + + // Encode instruction operands. + let Inst{19-16} = Sn{4-1}; + let Inst{7} = Sn{0}; + let Inst{15-12} = Rt; + + let Inst{6-5} = 0b00; + let Inst{3-0} = 0b0000; +} let neverHasSideEffects = 1 in { def VMOVRRD : AVConv3I<0b11000101, 0b1011, @@ -883,29 +909,29 @@ def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin), // let neverHasSideEffects = 1 in { -def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, - (outs DPR:$dst), (ins DPR:$false, DPR:$true), - IIC_fpUNA64, "vmov", ".f64\t$dst, $true", - [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>, - RegConstraint<"$false = $dst">; +def VMOVDcc : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", + [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, + RegConstraint<"$Dn = $Dd">; -def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, - (outs SPR:$dst), (ins SPR:$false, SPR:$true), - IIC_fpUNA32, "vmov", ".f32\t$dst, $true", - [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>, - RegConstraint<"$false = $dst">; +def VMOVScc : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", + [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, + RegConstraint<"$Sn = $Sd">; -def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, - (outs DPR:$dst), (ins DPR:$false, DPR:$true), - IIC_fpUNA64, "vneg", ".f64\t$dst, $true", - [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>, - RegConstraint<"$false = $dst">; +def VNEGDcc : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", + [/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, + RegConstraint<"$Dn = $Dd">; -def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0, - (outs SPR:$dst), (ins SPR:$false, SPR:$true), - IIC_fpUNA32, "vneg", ".f32\t$dst, $true", - [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>, - RegConstraint<"$false = $dst">; +def VNEGScc : ASuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", + [/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, + RegConstraint<"$Sn = $Sd">; } // neverHasSideEffects //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/ARM/simple-fp-encoding.ll b/llvm/test/MC/ARM/simple-fp-encoding.ll index 99b479bc7762..e9ece3529cf3 100644 --- a/llvm/test/MC/ARM/simple-fp-encoding.ll +++ b/llvm/test/MC/ARM/simple-fp-encoding.ll @@ -1,4 +1,4 @@ -;RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s +; RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s ; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests @@ -275,27 +275,27 @@ entry: ret float %add } -define double @f94(double %a, double %b, double %c) nounwind readnone { +define double @f92(double %a, double %b, double %c) nounwind readnone { entry: -; CHECK: f94 +; CHECK: f92 ; CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee] %mul = fmul double %a, %b %sub = fsub double %c, %mul ret double %sub } -define float @f95(float %a, float %b, float %c) nounwind readnone { +define float @f93(float %a, float %b, float %c) nounwind readnone { entry: -; CHECK: f95 +; CHECK: f93 ; CHECK: vmls.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x00,0xee] %mul = fmul float %a, %b %sub = fsub float %c, %mul ret float %sub } -define double @f96(double %a, double %b, double %c) nounwind readnone { +define double @f94(double %a, double %b, double %c) nounwind readnone { entry: -; CHECK: f96 +; CHECK: f94 ; CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee] %mul = fmul double %a, %b %sub = fsub double -0.000000e+00, %mul @@ -303,9 +303,9 @@ entry: ret double %sub3 } -define float @f97(float %a, float %b, float %c) nounwind readnone { +define float @f95(float %a, float %b, float %c) nounwind readnone { entry: -; CHECK: f97 +; CHECK: f95 ; CHECK: vnmla.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x10,0xee] %mul = fmul float %a, %b %sub = fsub float -0.000000e+00, %mul @@ -313,18 +313,18 @@ entry: ret float %sub3 } -define double @f92(double %a, double %b, double %c) nounwind readnone { +define double @f96(double %a, double %b, double %c) nounwind readnone { entry: -; CHECK: f92 +; CHECK: f96 ; CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee] %mul = fmul double %a, %b %sub = fsub double %mul, %c ret double %sub } -define float @f93(float %a, float %b, float %c) nounwind readnone { +define float @f97(float %a, float %b, float %c) nounwind readnone { entry: -; CHECK: f93 +; CHECK: f97 ; CHECK: vnmls.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x10,0xee] %mul = fmul float %a, %b %sub = fsub float %mul, %c @@ -333,6 +333,38 @@ entry: ; FIXME: Check for fmstat instruction. + +define double @f98(double %a, i32 %i) nounwind readnone { +entry: + %cmp = icmp eq i32 %i, 3 + br i1 %cmp, label %return, label %if.end + +if.end: ; preds = %entry +; CHECK: f98 +; CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] + %sub = fsub double -0.000000e+00, %a + ret double %sub + +return: ; preds = %entry + ret double %a +} + +define float @f99(float %a, i32 %i) nounwind readnone { +entry: + %cmp = icmp eq i32 %i, 3 + br i1 %cmp, label %if.end, label %return + +if.end: ; preds = %entry +; CHECK: f99 +; CHECK: vmovne r0, s0 @ encoding: [0x10,0x0a,0x10,0x1e] + %sub = fsub float -0.000000e+00, %a + ret float %sub + +return: ; preds = %entry + ret float %a +} + + define i32 @f100() nounwind readnone { entry: ; CHECK: f100 @@ -368,3 +400,26 @@ entry: %add = fadd float %a, 3.000000e+00 ret float %add } + +define void @f104(float %a, float %b, float %c, float %d, float %e, float %f) nounwind { +entry: +; CHECK: f104 +; CHECK: vmov s2, r0 @ encoding: [0x10,0x0a,0x01,0xee] +; CHECK: vmov s3, r1 @ encoding: [0x90,0x1a,0x01,0xee] +; CHECK: vmov s4, r2 @ encoding: [0x10,0x2a,0x02,0xee] +; CHECK: vmov s5, r3 @ encoding: [0x90,0x3a,0x02,0xee] + %conv = fptosi float %a to i32 + %conv2 = fptosi float %b to i32 + %conv4 = fptosi float %c to i32 + %conv6 = fptosi float %d to i32 + %conv8 = fptosi float %e to i32 + %conv10 = fptosi float %f to i32 + tail call void @g104(i32 %conv, i32 %conv2, i32 %conv4, i32 %conv6, i32 %conv8, i32 %conv10) nounwind +; CHECK: vmov r0, s2 @ encoding: [0x10,0x0a,0x11,0xee] +; CHECK: vmov r1, s3 @ encoding: [0x90,0x1a,0x11,0xee] +; CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee] +; CHECK: vmov r3, s5 @ encoding: [0x90,0x3a,0x12,0xee] + ret void +} + +declare void @g104(i32, i32, i32, i32, i32, i32)