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Add XTEST codegen support 

llvm-svn: 178083
This commit is contained in:
Michael Liao 2013-03-26 22:47:01 +00:00
parent e344ec919f
commit 03f9ad0e67
6 changed files with 35 additions and 1 deletions
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2
llvm/include/llvm/IR/IntrinsicsX86.td
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@ -2570,4 +2570,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Intrinsic<[], [], []>;
def int_x86_xabort : GCCBuiltin<"__builtin_ia32_xabort">,
Intrinsic<[], [llvm_i8_ty], [IntrNoReturn]>;
def int_x86_xtest : GCCBuiltin<"__builtin_ia32_xtest">,
Intrinsic<[llvm_i32_ty], [], []>;
}

13
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -10931,6 +10931,18 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
SDValue(Result.getNode(), 2));
}
// XTEST intrinsics.
case Intrinsic::x86_xtest: {
SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
DAG.getConstant(X86::COND_NE, MVT::i8),
InTrans);
SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
Ret, SDValue(InTrans.getNode(), 1));
}
}
}
@ -12772,6 +12784,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
case X86ISD::XTEST: return "X86ISD::XTEST";
}
}

3
llvm/lib/Target/X86/X86ISelLowering.h
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@ -360,6 +360,9 @@ namespace llvm {
PCMPISTRI,
PCMPESTRI,
// XTEST - Test if in transactional execution.
XTEST,
// ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
// ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
// Atomic 64-bit binary operations.

1
llvm/lib/Target/X86/X86InstrInfo.td
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@ -604,6 +604,7 @@ def HasBMI : Predicate<"Subtarget->hasBMI()">;
def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
def HasRTM : Predicate<"Subtarget->hasRTM()">;
def HasHLE : Predicate<"Subtarget->hasHLE()">;
def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
def HasADX : Predicate<"Subtarget->hasADX()">;
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;

6
llvm/lib/Target/X86/X86InstrTSX.td
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@ -15,6 +15,9 @@
//===----------------------------------------------------------------------===//
// TSX instructions
def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
[SDNPHasChain, SDNPSideEffect]>;
let usesCustomInserter = 1 in
def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
"# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
@ -28,7 +31,8 @@ def XEND : I<0x01, MRM_D5, (outs), (ins),
"xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
let Defs = [EFLAGS] in
def XTEST : I<0x01, MRM_D6, (outs), (ins), "xtest", []>, TB, Requires<[HasRTM]>;
def XTEST : I<0x01, MRM_D6, (outs), (ins),
"xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
"xabort\t$imm",

11
llvm/test/CodeGen/X86/xtest.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llc < %s -march=x86-64 -mattr=+rtm | FileCheck %s
declare i32 @llvm.x86.xtest() nounwind
define i32 @test_xtest() nounwind uwtable {
entry:
%0 = tail call i32 @llvm.x86.xtest() nounwind
ret i32 %0
; CHECK: test_xtest
; CHECK: xtest
}