Reversed revision 229706. The reason is regression, which is caused by the
usage of instruction ADDU16 by CodeGen. For this instruction an improper register is allocated, i.e. the register that is not from register set defined for the instruction. llvm-svn: 230053
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@ -642,10 +642,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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LW_FM_MM<0xc>;
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LW_FM_MM<0xc>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
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def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
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ADD_FM_MM<0, 0x150>;
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def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
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def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
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ADD_FM_MM<0, 0x1d0>;
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def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
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def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
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def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
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def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
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def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
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def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
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@ -1140,13 +1140,12 @@ def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
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xor>,
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xor>,
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ADDI_FM<0xe>;
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ADDI_FM<0xe>;
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def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
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def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
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let AdditionalPredicates = [NotInMicroMips] in {
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/// Arithmetic Instructions (3-Operand, R-Type)
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
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def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
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ADD_FM<0, 0x21>;
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ADD_FM<0, 0x21>;
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def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
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def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
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ADD_FM<0, 0x23>;
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ADD_FM<0, 0x23>;
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}
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let Defs = [HI0, LO0] in
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let Defs = [HI0, LO0] in
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def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
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def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
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ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
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ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
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@ -1,18 +0,0 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
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; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
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define i32 @main() {
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entry:
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%retval = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32* %b, align 4
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%1 = load i32* %c, align 4
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%add = add nsw i32 %0, %1
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store i32 %add, i32* %a, align 4
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ret i32 0
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}
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; CHECK: addu16
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@ -1,18 +0,0 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
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; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
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define i32 @main() {
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entry:
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%retval = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32* %b, align 4
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%1 = load i32* %c, align 4
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%sub = sub nsw i32 %0, %1
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store i32 %sub, i32* %a, align 4
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ret i32 0
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}
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; CHECK: subu16
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