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Redefine multiply and divide instructions. 

llvm-svn: 142211
This commit is contained in:
Akira Hatanaka 2011-10-17 18:21:24 +00:00
parent 2736bbc09e
commit 0317b65367
2 changed files with 26 additions and 25 deletions
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17
llvm/lib/Target/Mips/Mips64InstrInfo.td
View File

@ -52,17 +52,10 @@ class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
CPU64Regs>;
// Mul, Div
let Defs = [HI64, LO64] in {
let isCommutable = 1 in
class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>:
FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
!strconcat(instr_asm, "\t$a, $b"), [], itin>;
class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
!strconcat(instr_asm, "\t$$zero, $a, $b"),
[(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
}
Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
// Move from Hi/Lo
let shamt = 0 in {
@ -159,8 +152,8 @@ def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
/// Multiply and Divide Instructions.
def DMULT : Mul64<0x1c, "dmult", IIImul>;
def DMULTu : Mul64<0x1d, "dmultu", IIImul>;
def DMULT : Mult64<0x1c, "dmult", IIImul>;
def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;

30
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -461,24 +461,32 @@ let isCall=1, hasDelaySlot=1,
}
// Mul, Div
class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
FR<0x00, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
RegisterClass RC, list<Register> DefRegs>:
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
let rd = 0;
let shamt = 0;
let isCommutable = 1;
let Defs = [HI, LO];
let Defs = DefRegs;
}
class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
FR<0x00, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
RegisterClass RC, list<Register> DefRegs>:
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$$zero, $rs, $rt"),
[(op CPURegs:$rs, CPURegs:$rt)], itin> {
[(op RC:$rs, RC:$rt)], itin> {
let rd = 0;
let shamt = 0;
let Defs = [HI, LO];
let Defs = DefRegs;
}
class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
// Move from Hi/Lo
class MoveFromLOHI<bits<6> func, string instr_asm>:
FR<0x00, func, (outs CPURegs:$rd), (ins),
@ -726,10 +734,10 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1,
"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
/// Multiply and Divide Instructions.
def MULT : Mul<0x18, "mult", IIImul>;
def MULTu : Mul<0x19, "multu", IIImul>;
def SDIV : Div<MipsDivRem, 0x1a, "div", IIIdiv>;
def UDIV : Div<MipsDivRemU, 0x1b, "divu", IIIdiv>;
def MULT : Mult32<0x18, "mult", IIImul>;
def MULTu : Mult32<0x19, "multu", IIImul>;
def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
let Defs = [HI] in
def MTHI : MoveToLOHI<0x11, "mthi">;