diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index a135667beaac..4ed110e66635 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13362,7 +13362,8 @@ PPCTargetLowering::getConstraintType(StringRef Constraint) const {
   } else if (Constraint == "wc") { // individual CR bits.
     return C_RegisterClass;
   } else if (Constraint == "wa" || Constraint == "wd" ||
-             Constraint == "wf" || Constraint == "ws") {
+             Constraint == "wf" || Constraint == "ws" ||
+             Constraint == "wi") {
     return C_RegisterClass; // VSX registers.
   }
   return TargetLowering::getConstraintType(Constraint);
@@ -13392,6 +13393,8 @@ PPCTargetLowering::getSingleConstraintMatchWeight(
     return CW_Register;
   else if (StringRef(constraint) == "ws" && type->isDoubleTy())
     return CW_Register;
+  else if (StringRef(constraint) == "wi" && type->isIntegerTy(64))
+    return CW_Register; // just hold 64-bit integers data.
 
   switch (*constraint) {
   default:
@@ -13474,7 +13477,8 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     // An individual CR bit.
     return std::make_pair(0U, &PPC::CRBITRCRegClass);
   } else if ((Constraint == "wa" || Constraint == "wd" ||
-             Constraint == "wf") && Subtarget.hasVSX()) {
+             Constraint == "wf" || Constraint == "wi") &&
+             Subtarget.hasVSX()) {
     return std::make_pair(0U, &PPC::VSRCRegClass);
   } else if (Constraint == "ws" && Subtarget.hasVSX()) {
     if (VT == MVT::f32 && Subtarget.hasP8Vector())
diff --git a/llvm/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll b/llvm/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll
index 9de6358427d1..0ebb44930658 100644
--- a/llvm/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll
+++ b/llvm/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll
@@ -12,6 +12,21 @@ entry:
 ; CHECK: #NO_APP
 }
 
+define signext i32 @foo1(<4 x float> %__A) {
+entry:
+  %0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw  $1,$1;\0Amfvsrd  $0,${1:x};\0A", "=r,=&^wi,^wa"(<4 x float> %__A)
+  %asmresult = extractvalue { i32, <4 x float> } %0, 0
+  ret i32 %asmresult
+
+; CHECK: #APP
+; CHECK: xxsldwi vs0, v2, v2, 3
+; CHECK: xscvspdp f0, f0
+; CEHCK: fctiw f0, f0
+; CHECK: mffprd r3, f0
+; CEHCK: extsw r3, r3
+; CHECK: #NO_APP
+}
+
 define double @test() {
   entry:
     %0 = tail call double asm "mtvsrd ${0:x}, 1", "=^ws,~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14}"()
diff --git a/llvm/test/CodeGen/PowerPC/vec-asm-disabled.ll b/llvm/test/CodeGen/PowerPC/vec-asm-disabled.ll
index 333ccce6b89f..614f3e3f03a0 100644
--- a/llvm/test/CodeGen/PowerPC/vec-asm-disabled.ll
+++ b/llvm/test/CodeGen/PowerPC/vec-asm-disabled.ll
@@ -10,5 +10,14 @@ entry:
 ; CHECK: error: couldn't allocate output register for constraint 'wd'
 }
 
+define signext i32 @testi2(<4 x float> %__A) #0 {
+entry:
+  %0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3", "=^wi,=&^wi,^wi"(<4 x float> %__A) #0
+  %asmresult = extractvalue { i32, <4 x float> } %0, 0
+  ret i32 %asmresult
+
+; CHECK: error: couldn't allocate output register for constraint 'wi'
+}
+
 attributes #0 = { nounwind "target-features"="-vsx" }