R600/SI: Fix simple-loop.ll test

llvm-svn: 226596
This commit is contained in:
Tom Stellard 2015-01-20 19:33:02 +00:00
parent 0d49117769
commit 021053f500
3 changed files with 9 additions and 6 deletions

View File

@ -99,7 +99,9 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
ScratchOffsetFI = FrameInfo->CreateSpillStackObject(4,4);
BuildMI(*Entry, I, DL, TII->get(AMDGPU::SI_SPILL_S32_SAVE))
.addReg(ScratchOffsetPreloadReg)
.addFrameIndex(ScratchOffsetFI);
.addFrameIndex(ScratchOffsetFI)
.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
.addReg(AMDGPU::SGPR0, RegState::Undef);
}
@ -116,7 +118,8 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
MachineBasicBlock &MBB = *BI;
// Add the scratch offset reg as a live-in so that the register scavenger
// doesn't re-use it.
if (!MBB.isLiveIn(ScratchOffsetReg))
if (!MBB.isLiveIn(ScratchOffsetReg) &&
ScratchOffsetReg != AMDGPU::NoRegister)
MBB.addLiveIn(ScratchOffsetReg);
RS.enterBasicBlock(&MBB);
@ -173,8 +176,8 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
ScratchOffsetReg)
.addFrameIndex(ScratchOffsetFI)
.addReg(AMDGPU::NoRegister)
.addReg(AMDGPU::NoRegister);
.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
.addReg(AMDGPU::SGPR0, RegState::Undef);
} else if (!MBB.isLiveIn(ScratchOffsetReg)) {
MBB.addLiveIn(ScratchOffsetReg);
}
@ -191,6 +194,7 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
MI.getOperand(2).setIsUndef(false);
MI.getOperand(3).setReg(ScratchOffsetReg);
MI.getOperand(3).setIsUndef(false);
MI.getOperand(3).setIsKill(false);
MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));

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@ -142,7 +142,7 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
.addReg(SubReg, getDefRegState(IsLoad))
.addReg(ScratchRsrcReg, getKillRegState(IsKill))
.addImm(Offset)
.addReg(SOffset, getKillRegState(IsKill))
.addReg(SOffset)
.addImm(0) // glc
.addImm(0) // slc
.addImm(0) // tfe

View File

@ -1,4 +1,3 @@
; XFAIL: *
; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s
; CHECK-LABEL: {{^}}test_loop: