AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.
We couldn't cope if the first mask element was UNDEF before, which isn't ideal. llvm-svn: 206588
This commit is contained in:
Tim Northover
parent
191ebd874f
commit
01f315a556
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@ -3945,11 +3945,13 @@ static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
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unsigned NumElts = VT.getVectorNumElements();
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ReverseEXT = false;
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// Assume that the first shuffle index is not UNDEF. Fail if it is.
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if (M[0] < 0)
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return false;
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Imm = M[0];
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// Look for the first non-undef choice and count backwards from
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// that. E.g. <-1, -1, 3, ...> means that an EXT must start at 3 - 2 = 1. This
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// guarantees that at least one index is correct.
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const int *FirstRealElt =
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std::find_if(M.begin(), M.end(), [](int Elt) { return Elt >= 0; });
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assert(FirstRealElt != M.end() && "Completely UNDEF shuffle? Why bother?");
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Imm = *FirstRealElt - (FirstRealElt - M.begin());
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// If this is a VEXT shuffle, the immediate value is the index of the first
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// element. The other shuffle indices must be the successive elements after
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@ -1,4 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; arm64 has a separate copy due to intrinsics
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define <4 x i32> @copyTuple.QPair(i8* %a, i8* %b) {
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; CHECK-LABEL: copyTuple.QPair:
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@ -1,221 +1,222 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK: test_vext_s8:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2
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; CHECK-LABEL: test_vext_s8:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
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entry:
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%vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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ret <8 x i8> %vext
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}
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define <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK: test_vext_s16:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x6
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; CHECK-LABEL: test_vext_s16:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
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entry:
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%vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
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ret <4 x i16> %vext
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}
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define <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK: test_vext_s32:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x4
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; CHECK-LABEL: test_vext_s32:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
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entry:
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%vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2>
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ret <2 x i32> %vext
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}
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define <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) {
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; CHECK: test_vext_s64:
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; CHECK-LABEL: test_vext_s64:
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entry:
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%vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0>
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ret <1 x i64> %vext
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}
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define <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK: test_vextq_s8:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x2
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; CHECK-LABEL: test_vextq_s8:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
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entry:
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%vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
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ret <16 x i8> %vext
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}
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define <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK: test_vextq_s16:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6
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; CHECK-LABEL: test_vextq_s16:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
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entry:
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%vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
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ret <8 x i16> %vext
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}
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define <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK: test_vextq_s32:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x4
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; CHECK-LABEL: test_vextq_s32:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
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entry:
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%vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
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ret <4 x i32> %vext
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}
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define <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK: test_vextq_s64:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x8
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; CHECK-LABEL: test_vextq_s64:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
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entry:
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%vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
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ret <2 x i64> %vext
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}
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define <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK: test_vext_u8:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2
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; CHECK-LABEL: test_vext_u8:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
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entry:
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%vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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ret <8 x i8> %vext
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}
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define <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK: test_vext_u16:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x6
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; CHECK-LABEL: test_vext_u16:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
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entry:
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%vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
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ret <4 x i16> %vext
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}
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define <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK: test_vext_u32:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x4
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; CHECK-LABEL: test_vext_u32:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
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entry:
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%vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2>
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ret <2 x i32> %vext
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}
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define <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) {
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; CHECK: test_vext_u64:
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; CHECK-LABEL: test_vext_u64:
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entry:
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%vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0>
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ret <1 x i64> %vext
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}
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define <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK: test_vextq_u8:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x2
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; CHECK-LABEL: test_vextq_u8:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
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entry:
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%vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
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ret <16 x i8> %vext
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}
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define <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK: test_vextq_u16:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6
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; CHECK-LABEL: test_vextq_u16:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
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entry:
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%vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
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ret <8 x i16> %vext
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}
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define <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK: test_vextq_u32:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x4
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; CHECK-LABEL: test_vextq_u32:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
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entry:
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%vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
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ret <4 x i32> %vext
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}
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define <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK: test_vextq_u64:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x8
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; CHECK-LABEL: test_vextq_u64:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
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entry:
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%vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
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ret <2 x i64> %vext
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}
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define <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) {
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; CHECK: test_vext_f32:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x4
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; CHECK-LABEL: test_vext_f32:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
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entry:
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%vext = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 2>
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ret <2 x float> %vext
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}
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define <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK: test_vext_f64:
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; CHECK-LABEL: test_vext_f64:
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entry:
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%vext = shufflevector <1 x double> %a, <1 x double> %b, <1 x i32> <i32 0>
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ret <1 x double> %vext
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}
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define <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) {
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; CHECK: test_vextq_f32:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x4
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; CHECK-LABEL: test_vextq_f32:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
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entry:
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%vext = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
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ret <4 x float> %vext
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}
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define <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) {
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; CHECK: test_vextq_f64:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x8
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; CHECK-LABEL: test_vextq_f64:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
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entry:
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%vext = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
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ret <2 x double> %vext
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}
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define <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK: test_vext_p8:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2
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; CHECK-LABEL: test_vext_p8:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
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entry:
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%vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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ret <8 x i8> %vext
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}
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define <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK: test_vext_p16:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x6
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; CHECK-LABEL: test_vext_p16:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
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entry:
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%vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
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ret <4 x i16> %vext
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}
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define <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK: test_vextq_p8:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x2
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; CHECK-LABEL: test_vextq_p8:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
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entry:
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%vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
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ret <16 x i8> %vext
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}
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define <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK: test_vextq_p16:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6
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; CHECK-LABEL: test_vextq_p16:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
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entry:
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%vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
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ret <8 x i16> %vext
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}
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define <8 x i8> @test_undef_vext_s8(<8 x i8> %a) {
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; CHECK: test_undef_vext_s8:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2
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; CHECK-LABEL: test_undef_vext_s8:
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; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
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entry:
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%vext = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 10, i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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ret <8 x i8> %vext
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}
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define <16 x i8> @test_undef_vextq_s8(<16 x i8> %a) {
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; CHECK: test_undef_vextq_s8:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6
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; CHECK-LABEL: test_undef_vextq_s8:
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; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
|
||||
entry:
|
||||
%vext = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 20, i32 20, i32 20, i32 20, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 20, i32 20, i32 20, i32 20, i32 20>
|
||||
ret <16 x i8> %vext
|
||||
}
|
||||
|
||||
define <4 x i16> @test_undef_vext_s16(<4 x i16> %a) {
|
||||
; CHECK: test_undef_vext_s16:
|
||||
; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x4
|
||||
; CHECK-LABEL: test_undef_vext_s16:
|
||||
; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
|
||||
entry:
|
||||
%vext = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
|
||||
ret <4 x i16> %vext
|
||||
}
|
||||
|
||||
define <8 x i16> @test_undef_vextq_s16(<8 x i16> %a) {
|
||||
; CHECK: test_undef_vextq_s16:
|
||||
; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6
|
||||
; CHECK-LABEL: test_undef_vextq_s16:
|
||||
; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
|
||||
entry:
|
||||
%vext = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
|
||||
ret <8 x i16> %vext
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
|
||||
; arm64 has a separate copy due to intrinsics
|
||||
|
||||
define <4 x i32> @copyTuple.QPair(i32* %a, i32* %b) {
|
||||
; CHECK-LABEL: copyTuple.QPair:
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
|
||||
entry:
|
||||
%vld = tail call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2lane.v4i32.p0i32(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i64 1, i32* %a)
|
||||
%extract = extractvalue { <4 x i32>, <4 x i32> } %vld, 0
|
||||
%vld1 = tail call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i64 1, i32* %b)
|
||||
%vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld1, 0
|
||||
ret <4 x i32> %vld1.fca.0.extract
|
||||
}
|
||||
|
||||
define <4 x i32> @copyTuple.QTriple(i32* %a, i32* %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: copyTuple.QTriple:
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
|
||||
entry:
|
||||
%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3lane.v4i32.p0i32(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i64 1, i32* %a)
|
||||
%extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld, 0
|
||||
%vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, i64 1, i32* %b)
|
||||
%vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld1, 0
|
||||
ret <4 x i32> %vld1.fca.0.extract
|
||||
}
|
||||
|
||||
define <4 x i32> @copyTuple.QQuad(i32* %a, i32* %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: copyTuple.QQuad:
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
|
||||
; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
|
||||
entry:
|
||||
%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4lane.v4i32.p0i32(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, <4 x i32> %c, i64 1, i32* %a)
|
||||
%extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld, 0
|
||||
%vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i64 1, i32* %b)
|
||||
%vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld1, 0
|
||||
ret <4 x i32> %vld1.fca.0.extract
|
||||
}
|
||||
|
||||
declare { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2lane.v4i32.p0i32(<4 x i32>, <4 x i32>, i64, i32*)
|
||||
declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i64, i32*)
|
||||
declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i64, i32*)
|
||||
Loading…
Reference in New Issue