From 00dae6b22d2a573d83b77ca7d805e5c334ac3c30 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Wed, 3 Apr 2019 13:42:06 +0000 Subject: [PATCH] [DAGCombiner] loosen restrictions for moving shuffles after vector binop There are 3 changes to make this correspond to the same transform in instcombine: 1. Remove the legality check - we can't create anything less legal than we started with. 2. Ease the use restriction, so we only bail out if both operands have >1 use. 3. Ease the use restriction for binops with a repeated operand (eg, mul x, x). As discussed in D60150, there's a scalarization opportunity that will be made easier by allowing this transform more generally. llvm-svn: 357580 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 35 ++++++++++--------- llvm/test/CodeGen/AArch64/arm64-vext.ll | 6 ++-- llvm/test/CodeGen/ARM/reg_sequence.ll | 2 +- llvm/test/CodeGen/ARM/vlddup.ll | 18 +++++----- llvm/test/CodeGen/X86/2012-07-10-extload64.ll | 3 +- llvm/test/CodeGen/X86/scalarize-fp.ll | 35 +++++++------------ llvm/test/CodeGen/X86/trunc-ext-ld-st.ll | 23 ++++-------- 7 files changed, 52 insertions(+), 70 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 93d5bce9abf2..70b9afabfe38 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -18665,23 +18665,26 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { Opcode, SDLoc(LHS), LHS.getValueType(), Ops, N->getFlags())) return Fold; - // Type legalization might introduce new shuffles in the DAG. - // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask))) - // -> (shuffle (VBinOp (A, B)), Undef, Mask). - if (LegalTypes && isa(LHS) && - isa(RHS) && LHS.hasOneUse() && RHS.hasOneUse() && - LHS.getOperand(1).isUndef() && - RHS.getOperand(1).isUndef()) { - ShuffleVectorSDNode *SVN0 = cast(LHS); - ShuffleVectorSDNode *SVN1 = cast(RHS); - - if (SVN0->getMask().equals(SVN1->getMask())) { - SDValue UndefVector = LHS.getOperand(1); - SDValue NewBinOp = DAG.getNode(Opcode, SDLoc(N), VT, LHS.getOperand(0), + // Move unary shuffles with identical masks after a vector binop: + // VBinOp (shuffle A, Undef, Mask), (shuffle B, Undef, Mask)) + // --> shuffle (VBinOp A, B), Undef, Mask + // This does not require type legality checks because we are creating the + // same types of operations that are in the original sequence. We do have to + // restrict ops like integer div that have immediate UB (eg, div-by-zero) + // though. This code is adapted from the identical transform in instcombine. + if (Opcode != ISD::UDIV && Opcode != ISD::SDIV && + Opcode != ISD::UREM && Opcode != ISD::SREM && + Opcode != ISD::UDIVREM && Opcode != ISD::SDIVREM) { + auto *Shuf0 = dyn_cast(LHS); + auto *Shuf1 = dyn_cast(RHS); + if (Shuf0 && Shuf1 && Shuf0->getMask().equals(Shuf1->getMask()) && + LHS.getOperand(1).isUndef() && RHS.getOperand(1).isUndef() && + (LHS.hasOneUse() || RHS.hasOneUse() || LHS == RHS)) { + SDLoc DL(N); + SDValue NewBinOp = DAG.getNode(Opcode, DL, VT, LHS.getOperand(0), RHS.getOperand(0), N->getFlags()); - AddUsersToWorklist(N); - return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector, - SVN0->getMask()); + SDValue UndefV = LHS.getOperand(1); + return DAG.getVectorShuffle(VT, DL, NewBinOp, UndefV, Shuf0->getMask()); } } diff --git a/llvm/test/CodeGen/AArch64/arm64-vext.ll b/llvm/test/CodeGen/AArch64/arm64-vext.ll index c1edf1b2e9bf..f56e9e0f2b45 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vext.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vext.ll @@ -454,9 +454,9 @@ define <16 x i8> @vext1(<16 x i8> %_a) nounwind { define <2 x i64> @vext2(<2 x i64> %p0, <2 x i64> %p1) nounwind readnone ssp { entry: ; CHECK-LABEL: vext2: -; CHECK: ext.16b v1, v1, v1, #8 -; CHECK: ext.16b v0, v0, v0, #8 -; CHECK: add.2d v0, v0, v1 +; CHECK: add.2d v0, v0, v1 +; CHECK-NEXT: ext.16b v0, v0, v0, #8 +; CHECK-NEXT: ret %t0 = shufflevector <2 x i64> %p1, <2 x i64> undef, <2 x i32> %t1 = shufflevector <2 x i64> %p0, <2 x i64> undef, <2 x i32> %t2 = add <2 x i64> %t1, %t0 diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index 97bd654af0dc..a54dd0fe79f5 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -273,7 +273,7 @@ define arm_aapcs_vfpcc i32 @t10(float %x) nounwind { entry: ; CHECK-LABEL: t10: ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000 -; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]] +; CHECK: vmul.f32 q8, q9, d1[0] ; CHECK: vadd.f32 q8, q8, q8 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float %x, i32 1 ; <<4 x float>> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/vlddup.ll b/llvm/test/CodeGen/ARM/vlddup.ll index 72f9434fd10a..25637540befe 100644 --- a/llvm/test/CodeGen/ARM/vlddup.ll +++ b/llvm/test/CodeGen/ARM/vlddup.ll @@ -212,7 +212,7 @@ define <4 x float> @vld1dupQf(float* %A) nounwind { define <8 x i8> @vld2dupi8(i8* %A) nounwind { ;CHECK-LABEL: vld2dupi8: ;Check the (default) alignment value. -;CHECK: vld2.8 {d16[], d17[]}, [{{r[0-9]+|lr}}] +;CHECK: vld2.8 {d16[0], d17[0]}, [{{r[0-9]+|lr}}] %tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) %tmp1 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 0 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer @@ -283,7 +283,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind { ;CHECK-LABEL: vld2dupi16: ;Check that a power-of-two alignment smaller than the total size of the memory ;being loaded is ignored. -;CHECK: vld2.16 {d16[], d17[]}, [{{r[0-9]+|lr}}] +;CHECK: vld2.16 {d16[0], d17[0]}, [{{r[0-9]+|lr}}] %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer @@ -296,7 +296,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind { ;Check for a post-increment updating load. define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { ;CHECK-LABEL: vld2dupi16_update: -;CHECK: vld2.16 {d16[], d17[]}, [{{r[0-9]+|lr}}]! +;CHECK: vld2.16 {d16[0], d17[0]}, [{{r[0-9]+|lr}}]! %A = load i16*, i16** %ptr %A2 = bitcast i16* %A to i8* %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %A2, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) @@ -313,7 +313,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { define <4 x i16> @vld2dupi16_odd_update(i16** %ptr) nounwind { ;CHECK-LABEL: vld2dupi16_odd_update: ;CHECK: mov [[INC:r[0-9]+]], #6 -;CHECK: vld2.16 {d16[], d17[]}, [{{r[0-9]+|lr}}], [[INC]] +;CHECK: vld2.16 {d16[0], d17[0]}, [{{r[0-9]+|lr}}], [[INC]] %A = load i16*, i16** %ptr %A2 = bitcast i16* %A to i8* %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %A2, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) @@ -330,7 +330,7 @@ define <4 x i16> @vld2dupi16_odd_update(i16** %ptr) nounwind { define <2 x i32> @vld2dupi32(i8* %A) nounwind { ;CHECK-LABEL: vld2dupi32: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld2.32 {d16[], d17[]}, [{{r[0-9]+|lr}}:64] +;CHECK: vld2.32 {d16[0], d17[0]}, [{{r[0-9]+|lr}}:64] %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16) %tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer @@ -350,7 +350,7 @@ declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8*, <2 x ;Check for a post-increment updating load with register increment. define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld3dupi8_update: -;CHECK: vld3.8 {d16[], d17[], d18[]}, [{{r[0-9]+|lr}}], r1 +;CHECK: vld3.8 {d16[0], d17[0], d18[0]}, [{{r[0-9]+|lr}}], r1 %A = load i8*, i8** %ptr %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8) %tmp1 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 0 @@ -369,7 +369,7 @@ define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind { define <4 x i16> @vld3dupi16(i8* %A) nounwind { ;CHECK-LABEL: vld3dupi16: ;Check the (default) alignment value. VLD3 does not support alignment. -;CHECK: vld3.16 {d16[], d17[], d18[]}, [{{r[0-9]+|lr}}] +;CHECK: vld3.16 {d16[0], d17[0], d18[0]}, [{{r[0-9]+|lr}}] %tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8) %tmp1 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 0 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer @@ -391,7 +391,7 @@ declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8*, <4 x ;Check for a post-increment updating load. define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind { ;CHECK-LABEL: vld4dupi16_update: -;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [{{r[0-9]+|lr}}]! +;CHECK: vld4.16 {d16[0], d17[0], d18[0], d19[0]}, [{{r[0-9]+|lr}}]! %A = load i16*, i16** %ptr %A2 = bitcast i16* %A to i8* %tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8* %A2, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1) @@ -415,7 +415,7 @@ define <2 x i32> @vld4dupi32(i8* %A) nounwind { ;CHECK-LABEL: vld4dupi32: ;Check the alignment value. An 8-byte alignment is allowed here even though ;it is smaller than the total size of the memory being loaded. -;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [{{r[0-9]+|lr}}:64] +;CHECK: vld4.32 {d16[0], d17[0], d18[0], d19[0]}, [{{r[0-9]+|lr}}:64] %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8) %tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/X86/2012-07-10-extload64.ll b/llvm/test/CodeGen/X86/2012-07-10-extload64.ll index e1f9839340c3..60e3e3247311 100644 --- a/llvm/test/CodeGen/X86/2012-07-10-extload64.ll +++ b/llvm/test/CodeGen/X86/2012-07-10-extload64.ll @@ -5,9 +5,8 @@ define void @load_store(<4 x i16>* %in) { ; CHECK-LABEL: load_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero +; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: paddw %xmm0, %xmm0 -; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; CHECK-NEXT: movq %xmm0, (%eax) ; CHECK-NEXT: retl entry: diff --git a/llvm/test/CodeGen/X86/scalarize-fp.ll b/llvm/test/CodeGen/X86/scalarize-fp.ll index 5bc574b5948f..33c4154acfe7 100644 --- a/llvm/test/CodeGen/X86/scalarize-fp.ll +++ b/llvm/test/CodeGen/X86/scalarize-fp.ll @@ -379,16 +379,14 @@ define <4 x double> @load_fdiv_op0_constant_v4f64(double* %p) nounwind { define <2 x double> @fadd_splat_splat_v2f64(<2 x double> %vx, <2 x double> %vy) { ; SSE-LABEL: fadd_splat_splat_v2f64: ; SSE: # %bb.0: -; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0] -; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0] ; SSE-NEXT: addpd %xmm1, %xmm0 +; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0] ; SSE-NEXT: retq ; ; AVX-LABEL: fadd_splat_splat_v2f64: ; AVX: # %bb.0: -; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] -; AVX-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0] ; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] ; AVX-NEXT: retq %splatx = shufflevector <2 x double> %vx, <2 x double> undef, <2 x i32> zeroinitializer %splaty = shufflevector <2 x double> %vy, <2 x double> undef, <2 x i32> zeroinitializer @@ -399,19 +397,16 @@ define <2 x double> @fadd_splat_splat_v2f64(<2 x double> %vx, <2 x double> %vy) define <4 x double> @fsub_splat_splat_v4f64(double %x, double %y) { ; SSE-LABEL: fsub_splat_splat_v4f64: ; SSE: # %bb.0: -; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0] -; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0] ; SSE-NEXT: subpd %xmm1, %xmm0 +; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0] ; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: retq ; ; AVX-LABEL: fsub_splat_splat_v4f64: ; AVX: # %bb.0: +; AVX-NEXT: vsubpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] ; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 -; AVX-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0] -; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 -; AVX-NEXT: vsubpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: retq %vx = insertelement <4 x double> undef, double %x, i32 0 %vy = insertelement <4 x double> undef, double %y, i32 0 @@ -424,16 +419,14 @@ define <4 x double> @fsub_splat_splat_v4f64(double %x, double %y) { define <4 x float> @fmul_splat_splat_v4f32(<4 x float> %vx, <4 x float> %vy) { ; SSE-LABEL: fmul_splat_splat_v4f32: ; SSE: # %bb.0: -; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0] -; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0] ; SSE-NEXT: mulps %xmm1, %xmm0 +; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0] ; SSE-NEXT: retq ; ; AVX-LABEL: fmul_splat_splat_v4f32: ; AVX: # %bb.0: -; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0] -; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0] ; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0] ; AVX-NEXT: retq %splatx = shufflevector <4 x float> %vx, <4 x float> undef, <4 x i32> zeroinitializer %splaty = shufflevector <4 x float> %vy, <4 x float> undef, <4 x i32> zeroinitializer @@ -457,17 +450,15 @@ define <8 x float> @fdiv_splat_splat_v8f32(<8 x float> %vx, <8 x float> %vy) { ; ; AVX-LABEL: fdiv_splat_splat_v8f32: ; AVX: # %bb.0: +; AVX-NEXT: vrcpps %ymm1, %ymm2 +; AVX-NEXT: vmulps %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX-NEXT: vsubps %xmm1, %xmm3, %xmm1 +; AVX-NEXT: vmulps %xmm1, %xmm2, %xmm1 +; AVX-NEXT: vaddps %xmm1, %xmm2, %xmm1 +; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0] ; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 -; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0] -; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 -; AVX-NEXT: vrcpps %ymm1, %ymm2 -; AVX-NEXT: vmulps %ymm2, %ymm1, %ymm1 -; AVX-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] -; AVX-NEXT: vsubps %ymm1, %ymm3, %ymm1 -; AVX-NEXT: vmulps %ymm1, %ymm2, %ymm1 -; AVX-NEXT: vaddps %ymm1, %ymm2, %ymm1 -; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: retq %splatx = shufflevector <8 x float> %vx, <8 x float> undef, <8 x i32> zeroinitializer %splaty = shufflevector <8 x float> %vy, <8 x float> undef, <8 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/X86/trunc-ext-ld-st.ll b/llvm/test/CodeGen/X86/trunc-ext-ld-st.ll index f926cfa91119..c799441c13be 100644 --- a/llvm/test/CodeGen/X86/trunc-ext-ld-st.ll +++ b/llvm/test/CodeGen/X86/trunc-ext-ld-st.ll @@ -135,23 +135,12 @@ define void @load_4_i16(<4 x i16>* %A) { } define void @load_8_i8(<8 x i8>* %A) { -; SSE2-LABEL: load_8_i8: -; SSE2: # %bb.0: -; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero -; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; SSE2-NEXT: paddb %xmm0, %xmm0 -; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 -; SSE2-NEXT: packuswb %xmm0, %xmm0 -; SSE2-NEXT: movq %xmm0, (%rdi) -; SSE2-NEXT: retq -; -; SSE41-LABEL: load_8_i8: -; SSE41: # %bb.0: -; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero -; SSE41-NEXT: paddb %xmm0, %xmm0 -; SSE41-NEXT: packuswb %xmm0, %xmm0 -; SSE41-NEXT: movq %xmm0, (%rdi) -; SSE41-NEXT: retq +; CHECK-LABEL: load_8_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: paddb %xmm0, %xmm0 +; CHECK-NEXT: movq %xmm0, (%rdi) +; CHECK-NEXT: retq %T = load <8 x i8>, <8 x i8>* %A %G = add <8 x i8> %T, %T store <8 x i8> %G, <8 x i8>* %A