[WebAssembly] Annotate call and load/store immediates.
These will be used to guide the binary encoding of these immediates. llvm-svn: 290412
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@ -55,6 +55,10 @@ enum OperandType {
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OPERAND_F32IMM,
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OPERAND_F32IMM,
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/// 64-bit floating-point immediates.
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/// 64-bit floating-point immediates.
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OPERAND_F64IMM,
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OPERAND_F64IMM,
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/// 32-bit unsigned function indices.
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OPERAND_FUNCTION32,
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/// 32-bit unsigned memory offsets.
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OPERAND_OFFSET32,
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/// p2align immediate for load and store address alignment.
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/// p2align immediate for load and store address alignment.
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OPERAND_P2ALIGN,
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OPERAND_P2ALIGN,
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/// signature immediate for block/loop.
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/// signature immediate for block/loop.
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@ -26,7 +26,7 @@ def ADJCALLSTACKUP : I<(outs), (ins i32imm:$amt, i32imm:$amt2),
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} // isCodeGenOnly = 1
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} // isCodeGenOnly = 1
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multiclass CALL<WebAssemblyRegClass vt, string prefix> {
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multiclass CALL<WebAssemblyRegClass vt, string prefix> {
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def CALL_#vt : I<(outs vt:$dst), (ins i32imm:$callee, variable_ops),
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def CALL_#vt : I<(outs vt:$dst), (ins function32_op:$callee, variable_ops),
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[(set vt:$dst, (WebAssemblycall1 (i32 imm:$callee)))],
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[(set vt:$dst, (WebAssemblycall1 (i32 imm:$callee)))],
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!strconcat(prefix, "call\t$dst, $callee"),
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!strconcat(prefix, "call\t$dst, $callee"),
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0x10>;
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0x10>;
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@ -43,7 +43,7 @@ multiclass CALL<WebAssemblyRegClass vt, string prefix> {
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}
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}
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multiclass SIMD_CALL<ValueType vt, string prefix> {
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multiclass SIMD_CALL<ValueType vt, string prefix> {
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def CALL_#vt : SIMD_I<(outs V128:$dst), (ins i32imm:$callee, variable_ops),
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def CALL_#vt : SIMD_I<(outs V128:$dst), (ins function32_op:$callee, variable_ops),
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[(set (vt V128:$dst),
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[(set (vt V128:$dst),
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(WebAssemblycall1 (i32 imm:$callee)))],
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(WebAssemblycall1 (i32 imm:$callee)))],
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!strconcat(prefix, "call\t$dst, $callee"),
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!strconcat(prefix, "call\t$dst, $callee"),
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@ -73,7 +73,7 @@ let Uses = [SP32, SP64], isCall = 1 in {
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defm : SIMD_CALL<v4i32, "i32x4.">;
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defm : SIMD_CALL<v4i32, "i32x4.">;
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defm : SIMD_CALL<v4f32, "f32x4.">;
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defm : SIMD_CALL<v4f32, "f32x4.">;
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def CALL_VOID : I<(outs), (ins i32imm:$callee, variable_ops),
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def CALL_VOID : I<(outs), (ins function32_op:$callee, variable_ops),
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[(WebAssemblycall0 (i32 imm:$callee))],
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[(WebAssemblycall0 (i32 imm:$callee))],
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"call \t$callee", 0x10>;
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"call \t$callee", 0x10>;
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let isCodeGenOnly = 1 in {
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let isCodeGenOnly = 1 in {
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@ -86,6 +86,12 @@ def f32imm_op : Operand<f32>;
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let OperandType = "OPERAND_F64IMM" in
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let OperandType = "OPERAND_F64IMM" in
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def f64imm_op : Operand<f64>;
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def f64imm_op : Operand<f64>;
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let OperandType = "OPERAND_FUNCTION32" in
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def function32_op : Operand<i32>;
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let OperandType = "OPERAND_OFFSET32" in
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def offset32_op : Operand<i32>;
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let OperandType = "OPERAND_P2ALIGN" in {
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let OperandType = "OPERAND_P2ALIGN" in {
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def P2Align : Operand<i32> {
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def P2Align : Operand<i32> {
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let PrintMethod = "printWebAssemblyP2AlignOperand";
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let PrintMethod = "printWebAssemblyP2AlignOperand";
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@ -59,16 +59,16 @@ let Defs = [ARGUMENTS] in {
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// FIXME: When we can break syntax compatibility, reorder the fields in the
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// FIXME: When we can break syntax compatibility, reorder the fields in the
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// asmstrings to match the binary encoding.
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// asmstrings to match the binary encoding.
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def LOAD_I32 : I<(outs I32:$dst),
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def LOAD_I32 : I<(outs I32:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i32.load\t$dst, ${off}(${addr})${p2align}", 0x28>;
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[], "i32.load\t$dst, ${off}(${addr})${p2align}", 0x28>;
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def LOAD_I64 : I<(outs I64:$dst),
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def LOAD_I64 : I<(outs I64:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i64.load\t$dst, ${off}(${addr})${p2align}", 0x29>;
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[], "i64.load\t$dst, ${off}(${addr})${p2align}", 0x29>;
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def LOAD_F32 : I<(outs F32:$dst),
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def LOAD_F32 : I<(outs F32:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "f32.load\t$dst, ${off}(${addr})${p2align}", 0x2a>;
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[], "f32.load\t$dst, ${off}(${addr})${p2align}", 0x2a>;
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def LOAD_F64 : I<(outs F64:$dst),
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def LOAD_F64 : I<(outs F64:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "f64.load\t$dst, ${off}(${addr})${p2align}", 0x2b>;
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[], "f64.load\t$dst, ${off}(${addr})${p2align}", 0x2b>;
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} // Defs = [ARGUMENTS]
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} // Defs = [ARGUMENTS]
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@ -143,34 +143,34 @@ let Defs = [ARGUMENTS] in {
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// Extending load.
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// Extending load.
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def LOAD8_S_I32 : I<(outs I32:$dst),
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def LOAD8_S_I32 : I<(outs I32:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i32.load8_s\t$dst, ${off}(${addr})${p2align}", 0x2c>;
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[], "i32.load8_s\t$dst, ${off}(${addr})${p2align}", 0x2c>;
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def LOAD8_U_I32 : I<(outs I32:$dst),
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def LOAD8_U_I32 : I<(outs I32:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i32.load8_u\t$dst, ${off}(${addr})${p2align}", 0x2d>;
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[], "i32.load8_u\t$dst, ${off}(${addr})${p2align}", 0x2d>;
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def LOAD16_S_I32 : I<(outs I32:$dst),
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def LOAD16_S_I32 : I<(outs I32:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i32.load16_s\t$dst, ${off}(${addr})${p2align}", 0x2e>;
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[], "i32.load16_s\t$dst, ${off}(${addr})${p2align}", 0x2e>;
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def LOAD16_U_I32 : I<(outs I32:$dst),
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def LOAD16_U_I32 : I<(outs I32:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i32.load16_u\t$dst, ${off}(${addr})${p2align}", 0x2f>;
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[], "i32.load16_u\t$dst, ${off}(${addr})${p2align}", 0x2f>;
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def LOAD8_S_I64 : I<(outs I64:$dst),
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def LOAD8_S_I64 : I<(outs I64:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i64.load8_s\t$dst, ${off}(${addr})${p2align}", 0x30>;
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[], "i64.load8_s\t$dst, ${off}(${addr})${p2align}", 0x30>;
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def LOAD8_U_I64 : I<(outs I64:$dst),
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def LOAD8_U_I64 : I<(outs I64:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i64.load8_u\t$dst, ${off}(${addr})${p2align}", 0x31>;
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[], "i64.load8_u\t$dst, ${off}(${addr})${p2align}", 0x31>;
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def LOAD16_S_I64 : I<(outs I64:$dst),
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def LOAD16_S_I64 : I<(outs I64:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i64.load16_s\t$dst, ${off}(${addr})${p2align}", 0x32>;
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[], "i64.load16_s\t$dst, ${off}(${addr})${p2align}", 0x32>;
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def LOAD16_U_I64 : I<(outs I64:$dst),
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def LOAD16_U_I64 : I<(outs I64:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i64.load16_u\t$dst, ${off}(${addr})${p2align}", 0x33>;
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[], "i64.load16_u\t$dst, ${off}(${addr})${p2align}", 0x33>;
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def LOAD32_S_I64 : I<(outs I64:$dst),
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def LOAD32_S_I64 : I<(outs I64:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i64.load32_s\t$dst, ${off}(${addr})${p2align}", 0x34>;
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[], "i64.load32_s\t$dst, ${off}(${addr})${p2align}", 0x34>;
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def LOAD32_U_I64 : I<(outs I64:$dst),
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def LOAD32_U_I64 : I<(outs I64:$dst),
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(ins P2Align:$p2align, i32imm:$off, I32:$addr),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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[], "i64.load32_u\t$dst, ${off}(${addr})${p2align}", 0x35>;
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[], "i64.load32_u\t$dst, ${off}(${addr})${p2align}", 0x35>;
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} // Defs = [ARGUMENTS]
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} // Defs = [ARGUMENTS]
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@ -449,16 +449,16 @@ let Defs = [ARGUMENTS] in {
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// Basic store.
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// Basic store.
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// Note: WebAssembly inverts SelectionDAG's usual operand order.
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// Note: WebAssembly inverts SelectionDAG's usual operand order.
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def STORE_I32 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE_I32 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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I32:$val), [],
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I32:$val), [],
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"i32.store\t${off}(${addr})${p2align}, $val", 0x36>;
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"i32.store\t${off}(${addr})${p2align}, $val", 0x36>;
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def STORE_I64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE_I64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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I64:$val), [],
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I64:$val), [],
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"i64.store\t${off}(${addr})${p2align}, $val", 0x37>;
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"i64.store\t${off}(${addr})${p2align}, $val", 0x37>;
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def STORE_F32 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE_F32 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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F32:$val), [],
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F32:$val), [],
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"f32.store\t${off}(${addr})${p2align}, $val", 0x38>;
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"f32.store\t${off}(${addr})${p2align}, $val", 0x38>;
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def STORE_F64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE_F64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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F64:$val), [],
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F64:$val), [],
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"f64.store\t${off}(${addr})${p2align}, $val", 0x39>;
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"f64.store\t${off}(${addr})${p2align}, $val", 0x39>;
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@ -541,19 +541,19 @@ def : Pat<(store F64:$val, (WebAssemblywrapper texternalsym:$off)),
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let Defs = [ARGUMENTS] in {
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let Defs = [ARGUMENTS] in {
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// Truncating store.
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// Truncating store.
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def STORE8_I32 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE8_I32 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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I32:$val), [],
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I32:$val), [],
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"i32.store8\t${off}(${addr})${p2align}, $val", 0x3a>;
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"i32.store8\t${off}(${addr})${p2align}, $val", 0x3a>;
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def STORE16_I32 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE16_I32 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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I32:$val), [],
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I32:$val), [],
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"i32.store16\t${off}(${addr})${p2align}, $val", 0x3b>;
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"i32.store16\t${off}(${addr})${p2align}, $val", 0x3b>;
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def STORE8_I64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE8_I64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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I64:$val), [],
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I64:$val), [],
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"i64.store8\t${off}(${addr})${p2align}, $val", 0x3c>;
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"i64.store8\t${off}(${addr})${p2align}, $val", 0x3c>;
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def STORE16_I64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE16_I64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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I64:$val), [],
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I64:$val), [],
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"i64.store16\t${off}(${addr})${p2align}, $val", 0x3d>;
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"i64.store16\t${off}(${addr})${p2align}, $val", 0x3d>;
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def STORE32_I64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
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def STORE32_I64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
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I64:$val), [],
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I64:$val), [],
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"i64.store32\t${off}(${addr})${p2align}, $val", 0x3e>;
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"i64.store32\t${off}(${addr})${p2align}, $val", 0x3e>;
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