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Adjust register numbers in tests to compensate for the 

new lack of R2.

llvm-svn: 96407
This commit is contained in:
Dale Johannesen 2010-02-16 22:31:31 +00:00
parent cf01cbef16
commit 0062f7bf59
4 changed files with 14 additions and 14 deletions
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4
llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s | grep {subfc r3,r5,r4}
; RUN: llc < %s | grep {subfze r4,r2}
; RUN: llc < %s -regalloc=local | grep {subfc r2,r5,r4}
; RUN: llc < %s | grep {subfze r4,r6}
; RUN: llc < %s -regalloc=local | grep {subfc r6,r5,r4}
; RUN: llc < %s -regalloc=local | grep {subfze r3,r3}
; The first argument of subfc must not be the same as any other register.

4
llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
View File

@ -10,8 +10,8 @@ target triple = "powerpc-apple-darwin10.0"
define void @foo(i32 %y) nounwind ssp {
entry:
; CHECK: foo
; CHECK: add r2
; CHECK: 0(r2)
; CHECK: add r4
; CHECK: 0(r4)
%y_addr = alloca i32 ; <i32*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i32 %y, i32* %y_addr

6
llvm/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
View File

@ -1,9 +1,9 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
; RUN: grep {stw r3, 32751}
; RUN: grep {stw r4, 32751}
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
; RUN: grep {stw r3, 32751}
; RUN: grep {stw r4, 32751}
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
; RUN: grep {std r2, 9024}
; RUN: grep {std r3, 9024}
define void @test() {
store i32 0, i32* inttoptr (i64 48725999 to i32*)

14
llvm/test/CodeGen/PowerPC/indirectbr.ll
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@ -43,13 +43,13 @@ L2: ; preds = %L3, %bb2
L1: ; preds = %L2, %bb2
%res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
; PIC: addis r4, r2, ha16(L_BA4__foo_L5-"L1$pb")
; PIC: li r5, lo16(L_BA4__foo_L5-"L1$pb")
; PIC: add r4, r4, r5
; PIC: stw r4
; STATIC: li r2, lo16(L_BA4__foo_L5)
; STATIC: addis r2, r2, ha16(L_BA4__foo_L5)
; STATIC: stw r2
; PIC: addis r5, r4, ha16(L_BA4__foo_L5-"L1$pb")
; PIC: li r6, lo16(L_BA4__foo_L5-"L1$pb")
; PIC: add r5, r5, r6
; PIC: stw r5
; STATIC: li r4, lo16(L_BA4__foo_L5)
; STATIC: addis r4, r4, ha16(L_BA4__foo_L5)
; STATIC: stw r4
store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
ret i32 %res.3
}