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Add more constness to CodeGenRegisters. 

llvm-svn: 153667
This commit is contained in:
Jakob Stoklund Olesen 2012-03-29 18:03:59 +00:00
parent db365f38ea
commit 00296815c5
3 changed files with 7 additions and 7 deletions
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6
llvm/utils/TableGen/CodeGenRegisters.cpp
View File

@ -231,7 +231,7 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
} }
void void
CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet, CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
CodeGenRegBank &RegBank) const { CodeGenRegBank &RegBank) const {
assert(SubRegsComplete && "Must precompute sub-registers"); assert(SubRegsComplete && "Must precompute sub-registers");
std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices"); std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
@ -1095,7 +1095,7 @@ CodeGenRegBank::getRegClassForRegister(Record *R) {
} }
BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
SetVector<CodeGenRegister*> Set; SetVector<const CodeGenRegister*> Set;
// First add Regs with all sub-registers. // First add Regs with all sub-registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) { for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
@ -1110,7 +1110,7 @@ BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
for (unsigned i = 0; i != Set.size(); ++i) { for (unsigned i = 0; i != Set.size(); ++i) {
const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs(); const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
for (unsigned j = 0, e = SR.size(); j != e; ++j) { for (unsigned j = 0, e = SR.size(); j != e; ++j) {
CodeGenRegister *Super = SR[j]; const CodeGenRegister *Super = SR[j];
if (!Super->CoveredBySubRegs || Set.count(Super)) if (!Super->CoveredBySubRegs || Set.count(Super))
continue; continue;
// This new super-register is covered by its sub-registers. // This new super-register is covered by its sub-registers.

4
llvm/utils/TableGen/CodeGenRegisters.h
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@ -110,11 +110,11 @@ namespace llvm {
} }
// Add sub-registers to OSet following a pre-order defined by the .td file. // Add sub-registers to OSet following a pre-order defined by the .td file.
void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet, void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
CodeGenRegBank&) const; CodeGenRegBank&) const;
// List of super-registers in topological order, small to large. // List of super-registers in topological order, small to large.
typedef std::vector<CodeGenRegister*> SuperRegList; typedef std::vector<const CodeGenRegister*> SuperRegList;
// Get the list of super-registers. // Get the list of super-registers.
// This is only valid after computeDerivedInfo has visited all registers. // This is only valid after computeDerivedInfo has visited all registers.

4
llvm/utils/TableGen/RegisterInfoEmitter.cpp
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@ -306,7 +306,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
if (Reg.getSubRegs().empty()) if (Reg.getSubRegs().empty())
continue; continue;
// getSubRegs() orders by SubRegIndex. We want a topological order. // getSubRegs() orders by SubRegIndex. We want a topological order.
SetVector<CodeGenRegister*> SR; SetVector<const CodeGenRegister*> SR;
Reg.addSubRegsPreOrder(SR, RegBank); Reg.addSubRegsPreOrder(SR, RegBank);
OS << " /* " << Reg.getName() << "_SubRegsSet */ "; OS << " /* " << Reg.getName() << "_SubRegsSet */ ";
for (unsigned j = 0, je = SR.size(); j != je; ++j) for (unsigned j = 0, je = SR.size(); j != je; ++j)
@ -351,7 +351,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex
<< ", "; << ", ";
// FIXME not very nice to recalculate this // FIXME not very nice to recalculate this
SetVector<CodeGenRegister*> SR; SetVector<const CodeGenRegister*> SR;
Reg->addSubRegsPreOrder(SR, RegBank); Reg->addSubRegsPreOrder(SR, RegBank);
SubRegIndex += SR.size() + 1; SubRegIndex += SR.size() + 1;
} else } else