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hanchenye-llvm-project/llvm/test/CodeGen/X86/pr32241.ll

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[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s
define i32 @_Z3foov() {
; CHECK-LABEL: _Z3foov:
; CHECK: # BB#0: # %entry
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86] Remove AVX512 early out from X86FastISel::X86SelectCmp. This shouldn't be needed anymore since i1 isn't a legal type. llvm-svn: 316912
2017-10-30 22:50:11 +08:00
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 24
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movb $1, %al
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: movw $10959, {{[0-9]+}}(%esp) # imm = 0x2ACF
; CHECK-NEXT: movw $-15498, {{[0-9]+}}(%esp) # imm = 0xC376
; CHECK-NEXT: movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: cmpw $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp) # 1-byte Spill
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: jne .LBB0_2
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: # BB#1: # %lor.rhs
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: xorl %eax, %eax
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: movb %al, %cl
; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp) # 1-byte Spill
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .LBB0_2: # %lor.end
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al # 1-byte Reload
; CHECK-NEXT: movb $1, %cl
; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: movzbl %al, %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi # 4-byte Reload
[X86] Remove AVX512 early out from X86FastISel::X86SelectCmp. This shouldn't be needed anymore since i1 isn't a legal type. llvm-svn: 316912
2017-10-30 22:50:11 +08:00
; CHECK-NEXT: cmpl %edx, %esi
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: setl %al
; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: movzbl %al, %edx
; CHECK-NEXT: xorl $-1, %edx
; CHECK-NEXT: cmpl $0, %edx
; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp) # 1-byte Spill
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: jne .LBB0_4
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: # BB#3: # %lor.rhs4
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: xorl %eax, %eax
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: movb %al, %cl
; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp) # 1-byte Spill
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: jmp .LBB0_4
; CHECK-NEXT: .LBB0_4: # %lor.end5
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al # 1-byte Reload
; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: movzbl %al, %ecx
; CHECK-NEXT: movw %cx, %dx
; CHECK-NEXT: movw %dx, {{[0-9]+}}(%esp)
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
[X86] Remove AVX512 early out from X86FastISel::X86SelectCmp. This shouldn't be needed anymore since i1 isn't a legal type. llvm-svn: 316912
2017-10-30 22:50:11 +08:00
; CHECK-NEXT: addl $16, %esp
Reland "Correct dwarf unwind information in function epilogue for X86" Reland r317100 with minor fix regarding ComputeCommonTailLength function in BranchFolding.cpp. Skipping top CFI instructions block needs to executed on several more return points in ComputeCommonTailLength(). Original r317100 message: "Correct dwarf unwind information in function epilogue for X86" This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: - CFI instructions do not affect code generation - Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Changed CFI instructions so that they: - are duplicable - are not counted as instructions when tail duplicating or tail merging - can be compared as equal Added CFIInstrInserter pass: - analyzes each basic block to determine cfa offset and register valid at its entry and exit - verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors - inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. llvm-svn: 317579
2017-11-07 22:40:27 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86][AVX512] Make i1 illegal in the CodeGen This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
2017-05-19 20:35:15 +08:00
; CHECK-NEXT: popl %esi
Reland "Correct dwarf unwind information in function epilogue for X86" Reland r317100 with minor fix regarding ComputeCommonTailLength function in BranchFolding.cpp. Skipping top CFI instructions block needs to executed on several more return points in ComputeCommonTailLength(). Original r317100 message: "Correct dwarf unwind information in function epilogue for X86" This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: - CFI instructions do not affect code generation - Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Changed CFI instructions so that they: - are duplicable - are not counted as instructions when tail duplicating or tail merging - can be compared as equal Added CFIInstrInserter pass: - analyzes each basic block to determine cfa offset and register valid at its entry and exit - verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors - inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. llvm-svn: 317579
2017-11-07 22:40:27 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 4
[AVX-512] Add test case for PR32241. Fix coming in another commit. llvm-svn: 297573
2017-03-12 11:37:34 +08:00
; CHECK-NEXT: retl
entry:
%aa = alloca i16, align 2
%bb = alloca i16, align 2
%cc = alloca i16, align 2
store i16 10959, i16* %aa, align 2
store i16 -15498, i16* %bb, align 2
store i16 19417, i16* %cc, align 2
%0 = load i16, i16* %aa, align 2
%conv = zext i16 %0 to i32
%1 = load i16, i16* %cc, align 2
%tobool = icmp ne i16 %1, 0
br i1 %tobool, label %lor.end, label %lor.rhs
lor.rhs: ; preds = %entry
br label %lor.end
lor.end: ; preds = %lor.rhs, %entry
%2 = phi i1 [ true, %entry ], [ false, %lor.rhs ]
%conv1 = zext i1 %2 to i32
%cmp = icmp slt i32 %conv, %conv1
%conv2 = zext i1 %cmp to i32
%neg = xor i32 %conv2, -1
%tobool3 = icmp ne i32 %neg, 0
br i1 %tobool3, label %lor.end5, label %lor.rhs4
lor.rhs4: ; preds = %lor.end
br label %lor.end5
lor.end5: ; preds = %lor.rhs4, %lor.end
%3 = phi i1 [ true, %lor.end ], [ false, %lor.rhs4 ]
%conv6 = zext i1 %3 to i16
store i16 %conv6, i16* %bb, align 2
%4 = load i16, i16* %bb, align 2
%conv7 = zext i16 %4 to i32
ret i32 %conv7
}