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hanchenye-llvm-project/llvm/test/CodeGen/AVR/sext.ll

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[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
; RUN: llc < %s -march=avr | FileCheck %s
; sext R17:R16, R13
; mov r16, r13
; mov r17, r13
; lsl r17
; sbc r17, r17
define i16 @sext1(i8 %x, i8 %y) {
; CHECK-LABEL: sext1:
; CHECK: mov r24, r22
; CHECK: mov r25, r22
; CHECK: lsl r25
; CHECK: sbc r25, r25
%1 = sext i8 %y to i16
ret i16 %1
}
; sext R17:R16, R16
; mov r17, r16
; lsl r17
; sbc r17, r17
define i16 @sext2(i8 %x) {
; CHECK-LABEL: sext2:
; CHECK: mov r25, r24
; CHECK: lsl r25
; CHECK: sbc r25, r25
%1 = sext i8 %x to i16
ret i16 %1
}