hanchenye-llvm-project/clang/test/CodeGen/builtins-ppc-vsx.c

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[PowerPC] Initial VSX intrinsic support, with min/max for vector double Now that we have initial support for VSX, we can begin adding intrinsics for programmer access to VSX instructions. This patch performs the necessary enablement in the front end, and tests it by implementing intrinsics for minimum and maximum using the vector double data type. The main change in the front end is to no longer disallow "vector" and "double" in the same declaration (lib/Sema/DeclSpec.cpp), but "vector" and "long double" must still be disallowed. The new intrinsics are accessed via vec_max and vec_min with changes in lib/Headers/altivec.h. Note that for v4f32, we already access corresponding VMX builtins, but with VSX enabled we should use the forms that allow all 64 vector registers. The new built-ins are defined in include/clang/Basic/BuiltinsPPC.def. I've added a new test in test/CodeGen/builtins-ppc-vsx.c that is similar to, but much smaller than, builtins-ppc-altivec.c. This allows us to test VSX IR generation without duplicating CHECK lines for the existing bazillion Altivec tests. Since vector double is now legal when VSX is available, I've modified the error message, and changed where we test for it and for vector long double, since the target machine isn't visible in the old place. This serendipitously removed a not-pertinent warning about 'long' being deprecated when used with 'vector', when "vector long double" is encountered and we just want to issue an error. The existing tests test/Parser/altivec.c and test/Parser/cxx-altivec.cpp have been updated accordingly, and I've added test/Parser/vsx.c to verify that "vector double" is now legitimate with VSX enabled. There is a companion patch for LLVM. llvm-svn: 220989
2014-11-01 03:19:24 +08:00
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -faltivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
vector float vf = { -1.5, 2.5, -3.5, 4.5 };
vector double vd = { 3.5, -7.5 };
double d = 23.4;
vector float res_vf;
vector double res_vd;
double res_d;
void test1() {
// CHECK-LABEL: define void @test1
/* vec_max */
res_vf = vec_max(vf, vf);
// CHECK: @llvm.ppc.vsx.xvmaxsp
res_vd = vec_max(vd, vd);
// CHECK: @llvm.ppc.vsx.xvmaxdp
res_vf = vec_vmaxfp(vf, vf);
// CHECK: @llvm.ppc.vsx.xvmaxsp
/* vec_min */
res_vf = vec_min(vf, vf);
// CHECK: @llvm.ppc.vsx.xvminsp
res_vd = vec_min(vd, vd);
// CHECK: @llvm.ppc.vsx.xvmindp
res_vf = vec_vminfp(vf, vf);
// CHECK: @llvm.ppc.vsx.xvminsp
res_d = __builtin_vsx_xsmaxdp(d, d);
// CHECK: @llvm.ppc.vsx.xsmaxdp
res_d = __builtin_vsx_xsmindp(d, d);
// CHECK: @llvm.ppc.vsx.xsmindp
}