2006-05-15 06:18:28 +08:00
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//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMREGISTERINFO_H
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#define ARMREGISTERINFO_H
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#include "llvm/Target/MRegisterInfo.h"
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#include "ARMGenRegisterInfo.h.inc"
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namespace llvm {
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2007-01-19 15:51:42 +08:00
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class ARMSubtarget;
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2007-02-28 05:12:35 +08:00
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class TargetInstrInfo;
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class Type;
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struct ARMRegisterInfo : public ARMGenRegisterInfo {
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2006-11-28 07:37:22 +08:00
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const TargetInstrInfo &TII;
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2007-01-19 15:51:42 +08:00
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const ARMSubtarget &STI;
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private:
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/// FramePtr - ARM physical register used as frame ptr.
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unsigned FramePtr;
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public:
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ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
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2006-05-15 06:18:28 +08:00
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2007-01-19 15:51:42 +08:00
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// ARM::LR, return the number that it corresponds to (e.g. 14).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// Code Generation virtual methods...
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const;
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const;
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2006-05-15 06:18:28 +08:00
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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2007-10-05 09:32:41 +08:00
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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2007-10-19 06:40:57 +08:00
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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2007-10-19 05:29:24 +08:00
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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2007-10-05 09:32:41 +08:00
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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2007-03-20 16:09:38 +08:00
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, const MachineInstr *Orig) const;
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2007-01-19 15:51:42 +08:00
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MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
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int FrameIndex) const;
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2007-08-30 13:52:20 +08:00
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MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
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MachineInstr* LoadMI) const {
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return 0;
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}
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2007-07-14 22:06:15 +08:00
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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2006-05-18 08:12:58 +08:00
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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2006-05-18 08:12:58 +08:00
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2007-02-20 05:49:54 +08:00
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BitVector getReservedRegs(const MachineFunction &MF) const;
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2007-03-06 18:03:56 +08:00
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bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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2007-02-28 08:59:19 +08:00
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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2007-02-28 08:21:17 +08:00
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2007-01-23 08:57:47 +08:00
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bool hasFP(const MachineFunction &MF) const;
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2007-05-01 08:52:08 +08:00
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bool hasReservedCallFrame(MachineFunction &MF) const;
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2006-05-15 06:18:28 +08:00
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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2007-02-28 08:21:17 +08:00
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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2007-05-01 17:13:03 +08:00
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int SPAdj, RegScavenger *RS = NULL) const;
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2007-03-06 18:03:56 +08:00
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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2006-05-15 06:18:28 +08:00
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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2007-02-22 06:54:50 +08:00
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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};
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} // end namespace llvm
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#endif
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